Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage

  • Domenik Helms
  • Marko Hoyer
  • Wolfgang Nebel
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)


We present a blackbox approach to model leakage currents of RTL data-path components. The model inputs are temperature, V DD , body voltage of NMOS and PMOS and the bitvector at the input. Additionally, the model accepts a statistical Gaussian variation introduced by intra-die and systematic variation introduced by inter-die. Both variations can be given independently for each BSIM-level process parameter; in this work we evaluate variation of channel length, gate-oxide thickness and channel doping. Model output is the sum of subthreshold, gate, and pn-junction leakage. The evaluation of an RT component can be done in milliseconds and the result for the 45nm and 65nm BPTM technology is within 2% against single BSIM4.40 evaluation and within 5% against statistical BSIM4.40 evaluation assuming 1% variation of the process parameters.


Leakage Current Linear Parameter Regression Channel Doping Transistor Model Power Gating 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Domenik Helms
    • 1
  • Marko Hoyer
    • 1
  • Wolfgang Nebel
    • 2
  1. 1.OFFIS Research Institute 
  2. 2.University of OldenburgOldenburgGermany

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