QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis

  • Eslam Yahya
  • Marc Renaudin
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)


Asynchronous logic is a hot topic due to its interesting features of power saving, low noise and robustness to parameters variations. However, its performance analysis is relatively complex. In fact, the handshaking protocol strongly influences the performance of the pipelined architectures. This paper introduces verified Standard-Logic schematics for QDI asynchronous latches and analyzes their characteristics. Buffering capacity and protocol gain are defined and analyzed. Based on this analysis, reduced performance equations are first introduced. By means of the dependency graphs, a new formal method is then proposed to analyze the performance of asynchronous linear-pipeline. This methodology is used to derive general equations for each latch type. Contrarily to previously proposed methods, this method can be applied to any asynchronous linear-pipeline without restrictions on its functional block delays. Therefore, the contributions of this paper enable the designers to understand the benefits brought by the different asynchronous latches, to compare them and make the right choice according to their design constrains....


Cycle Time Dependency Graph Function Block Stage Number Reset Phase 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. Andrew Lines: Pipelined Asynchronous Circuits. Master Thesis (1995)Google Scholar
  2. Yahya, E., Renaudin, M.: Asynchronous Buffers Characteristics: Molding and Design. Research Report, TIMA-RR–06/-01–FR (2006)Google Scholar
  3. Fournier, J.J.A., Moore, S., Li, H., Mullins, R., Taylor, G.: Security Evaluation of Asynchronous Circuits. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 137–151. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  4. SparsØ, J., Furber, S.: Principles of Asynchronous Circuit Design. A System Perspective. Kluwer Academic Publishers, Dordrecht (2001)Google Scholar
  5. Renaudin, M., Leonardo, J.: Asynchronous Circuits Design: An Architectural Approach (2003)Google Scholar
  6. Beerel, P.A.: Asynchronous Circuits: An Increasingly Practical Design Solution. In: Proceedings of ISQED 2002. IEEE Computer Society, Los Alamitos (2002)Google Scholar
  7. Furber, S.B., Day, P.: Four-Phase Micropipline Latch Control Circuits. IEEE Transitions on VLSI Systems 4(2), 247–253 (1996)CrossRefGoogle Scholar
  8. Williams, T.: Latency and Throughput Tradeoffs in Self-Timed Speed-Independent Pipelines and Rings. Technical Report No. CSL-TR-90-431 (1990)Google Scholar
  9. Williams, T.: Perfoemance of Itrative Computation in Self-Timed Rings. Journal of VLSI Signal Processing 7, 17–31 (1994)CrossRefGoogle Scholar
  10. Van Berkel, C.H(K.), Josephs, M.B., Nowick, S.M.: Scanning the Technology. Applications of Asynchronous Circuits. Proceedings of the IEEE 87(2) (1999)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Eslam Yahya
    • 1
    • 2
  • Marc Renaudin
    • 1
  1. 1.TIMA LaboratoryCIS GroupGrenobleFrance
  2. 2.Banha High Institute of TechnologyBanhaEgypt

Personalised recommendations