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A Framework for Estimating Peak Power in Gate-Level Circuits

  • Diganchal Chakraborty
  • P. P. Chakrabarti
  • Arijit Mondal
  • Pallab Dasgupta
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)

Abstract

This paper presents a framework for estimation of peak power dissipation in gate level circuits. This measure can be used to make architectural or design style decisions during the VLSI synthesis process. The proposed method first builds a symbolic event list for every possible input and uses this as the database for computing the peak power estimate. A novel heuristic search based method is presented which works on this symbolic event list to estimate peak power. Experimental results on ISCAS’89 benchmarks demonstrate the proposed method to be effective on moderately large circuits.

Keywords

Peak Power Primary Input Binary Decision Diagram Partial Assignment Sequential Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Diganchal Chakraborty
    • 1
  • P. P. Chakrabarti
    • 1
  • Arijit Mondal
    • 1
  • Pallab Dasgupta
    • 1
  1. 1.Indian Institute of Technology KharagpurIndia

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