Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors

  • Toshinori Sato
  • Yuu Tanaka
  • Hidenori Sato
  • Toshimasa Funaki
  • Takenori Koushiro
  • Akihiro Chiyonobu
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)


The advance in semiconductor technologies has increased the number of transistors on a die, resulting in the continuous improvement in microprocessor performance. However, the increase in power consumption and hence in power density is about to stop the progress in microprocessor performance. While supply voltage reduction is commonly known as an effective technique for power savings, it increases gate delay and thus causes performance degradation. The increasing transistors can be utilized for maintaining performance while reducing power consumption. We are considering a speculative multithreaded execution on MultiCore processors. We propose to execute only the part of the program, which has the impact on program execution time, on power-hungry cores. In order to enable this, we divide the instruction stream into two streams. One is called speculation stream, which is the main part of a program and where speculation is applied. It is executed on power-hungry cores. The other is the verification stream, which verifies every speculation. It is executed on low-power cores. The energy consumption is reduced by the decrease in the execution time in the speculation stream and by the low-power execution in the verification stream. We call this technique Contrail architecture. The paper will present the energy efficiency of a Contrail processor based on detailed simulations.


Clock Frequency Improve Energy Efficiency Leakage Power MultiCore Processor Processor Performance 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Bhargava, R., John, L.: Latency and energy aware value prediction for high-frequency processors. In: 16th International Conference on Supercomputing (June 2002)Google Scholar
  2. 2.
    Borkar, S.: Microarchitecture and design challenges for gigascale integration. In: 37th International Symposium on Microarchitecture, Keynote (December 2004)Google Scholar
  3. 3.
    Chandrakasan, A.P., Brodersen, R.W.: Minimizing power consumption in digital CMOS circuits. Proceedings of IEEE 83(4) (April 1995)Google Scholar
  4. 4.
    Chaparro, P., Gonzalez, J., Gonzalez, A.: Thermal-effective clustered microarchitecture. In: 1st Workshop on Temperature Aware Computer System (June 2004)Google Scholar
  5. 5.
    Codrescu, L., Wills, D.: On dynamic speculative thread partitioning and the MEM-slicing algorithm. In: 8th International Conference on Parallel Architectures and Compilation Techniques (October 1999)Google Scholar
  6. 6.
    Edahiro, M., Matsushita, S., Yamashina, M., Nishi, N.: A single-chip multi-processor for smart terminals. IEEE Micro 20(4) (July-August 2000)Google Scholar
  7. 7.
    Fleischmann, M.: LongRun power management, white paper, Transmeta Corporation (January 2001) Google Scholar
  8. 8.
    Flynn, D.: Intelligent energy management: an SoC design based on ARM926EJ-S. In: 15th Hot Chips (August 2003) Google Scholar
  9. 9.
    Franklin, M.: Multiscalar processors. Kluwer Academic Publishers, Dordrecht (2003)MATHGoogle Scholar
  10. 10.
    Gochman, S., Ronen, R., Anati, I., Berkovits, A., Kurts, T., Naveh, A., Saeed, A., Sperber, Z., Valentine, R.C.: The Intel Pentium M processor: microarchitecture and performance. Intel Technology Journal 7(2) (May 2003)Google Scholar
  11. 11.
    Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, B.: MiBench: a free, commercially representative embedded benchmark suite. In: 4th Workshop on Workload Characterization (December 2001)Google Scholar
  12. 12.
    Kaneko, S., Sawai, K., Masui, N., Ishimi, K., Itou, T., Satou, M., Kondo, H., Okumura, N., Takata, Y., Takata, H., Sakugawa, M., Higuchi, T., Ohtani, S., Sakamoto, K., Ishikawa, N., Nakajima, M., Iwata, S., Hayase, K., Nakano, S., Nakazawa, S., Tomisawa, O., Shimizu, T.: A 600 MHz single-chip multiprocessor with 4.8 GB/s internal shared pipelined bus and 512 kB internal memory. In: International Solid State Circuits Conference (February 2005)Google Scholar
  13. 13.
    Kuroda, T., Fujita, T., Mita, S., Nagamatsu, T., Yoshioka, S., Sano, F., Norishima, M., Murota, M., Kato, M., Kinugasa, M., Kakumu, M., Sakurai, T.: A 0.9V, 150MHz, 10mW, 4mm2, 2-D discrete cosine transform core processor with variable-threshold-voltage scheme. In: International Solid State Circuit Conference (February 1996)Google Scholar
  14. 14.
    Larson, E., Chatterjee, S., Austin, T.: MASE: a novel infrastructure for detailed microarchitectural modeling. In: International Symposium on Performance Analysis of Systems and Software (November 2001) Google Scholar
  15. 15.
    Lipasti, M.H., Wilkerson, C.B., Shen, J.P.: Value locality and load value prediction. In: 7th International Conference on Architectural Support for Programming Languages and Operation Systems (October 1996) Google Scholar
  16. 16.
    Moreno, R., Pinuel, L., Del-Pino, S., Tirado, F.: A power perspective of value speculation for superscalar microprocessors. In: 19th International Conference on Computer Design (September 2000) Google Scholar
  17. 17.
    Pilla, M.L., da Costa, A.T., Franca, F.M.G., Navaux, P.O.A.: Predicting trace inputs with dynamic trace memoization: determining speedup upper bounds. In: 10th International Conference on Parallel Architectures and Compilation Techniques, WiP session (September 2001) Google Scholar
  18. 18.
    Rattner, J.: Electronics in the Internet age. In: 10th International Conference on Parallel Architectures and Compilation Techniques, Keynote (September 2001) Google Scholar
  19. 19.
    Sam, N.B., Burtscher, M.: On the energy-efficiency of speculative hardware. In: International Conference on Computing Frontiers (May 2005) Google Scholar
  20. 20.
    Sato, T., Arita, I.: Contrail processors for converting high-performance into energy-efficiency. In: 10th International Conference on Parallel Architectures and Compilation Techniques, WiP session (September 2001) Google Scholar
  21. 21.
    Shiota, T., Kawasaki, K., Kawabe, Y., Shibamoto, W., Sato, A., Hashimoto, T., Hayakawa, F., Tago, S., Okano, H., Nakamura, Y., Miyake, H., Suga, A., Takahashi, H.: A 51.2GOPS, 1.0GB/s-DMA single-chip multi-processor integrating quadruple 8-way VLIW processors. In: International Solid State Circuits Conference (February 2005) Google Scholar
  22. 22.
    Sundaramoorthy, K., Purser, Z., Rotenberg, E.: Slipstream processors: improving both performance and fault tolerance. In: 9th International Conference on Architectural Support for Programming Languages and Operating Systems (November 2000) Google Scholar
  23. 23.
    Tanaka, Y., Sato, T., Koushiro, T.: The potential in energy efficiency of a speculative chip-multiprocessor. In: 16th Symposium on Parallelism in Algorithms and Architectures (June 2004) Google Scholar
  24. 24.
    Torii, S., Suzuki, S., Tomonaga, H., Tokue, T., Sakai, J., Suzuki, N., Murakami, K., Hiraga, T., Shigemoto, K., Tatebe, Y., Obuchi, E., Kayama, N., Edahiro, E., Kusano, T., Nishi, N.: A 600MIPS 120mW 70A leakage triple-CPU mobile application processor chip. In: International Solid State Circuits Conference (February 2005) Google Scholar
  25. 25.
    Transmeta Corporation: LongRun2 technology,
  26. 26.
    Zilles, C., Sohi, G.S.: Master/slave speculative parallelization. In: 35th International Symposium on Microarchitecture (November 2002) Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Toshinori Sato
    • 1
  • Yuu Tanaka
    • 2
  • Hidenori Sato
    • 3
  • Toshimasa Funaki
    • 4
  • Takenori Koushiro
    • 5
  • Akihiro Chiyonobu
    • 4
  1. 1.System LSI Research CenterKyushu UniversityFukuokaJapan
  2. 2.Kyushu Railway CompanyFukuokaJapan
  3. 3.Seiko Epson CorporationSuwaJapan
  4. 4.Graduate School of Computer Science and System EngineeringKyushu Institute of TechnologyIizukaJapan
  5. 5.Toshiba CorporationKawasakiJapan

Personalised recommendations