Abstract
This paper presents a hardware technique to reduce both the static and dynamic power consumption in Functional Units of a 64-bit superscalar processor. We have studied the instructions that require an adder and we can conclude that, in 64-bit processors, there are many instructions that do not require a 64-bit adder, and that by knowing the type of operation we can also know what adder type this instruction requires. This is due that there are some types of instruction where one of the two source operands is always narrow. Our approach is based on substituting some of the 64-bit power-hungry adders by others of 32-bit and 24-bits lower power-consumption adders, and modifying the protocol in order to issue as much instructions as possible to those low power-consumption units incurring in a negligible performance penalty. We have tested four different configurations for the execution units in order to find which one obtains a higher reduction on power-consumption, preserving the performance of the processor. Our technique saves between 38,8% and a 54,1% of the power-consumption in the adders which is between 16,6% and a 23,1% of power-consumption in the execution units. This reduction is important because it can avoid the creation of a hot spot on the functional units.
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© 2006 Springer-Verlag Berlin Heidelberg
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Miñana, G., Hidalgo, J.I., Garnica, O., Lanchares, J., Colmenar, J.M., López, S. (2006). A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_50
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DOI: https://doi.org/10.1007/11847083_50
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
Online ISBN: 978-3-540-39097-8
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