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A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors

  • Guadalupe Miñana
  • José Ignacio Hidalgo
  • Oscar Garnica
  • Juan Lanchares
  • José Manuel Colmenar
  • Sonia López
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)

Abstract

This paper presents a hardware technique to reduce both the static and dynamic power consumption in Functional Units of a 64-bit superscalar processor. We have studied the instructions that require an adder and we can conclude that, in 64-bit processors, there are many instructions that do not require a 64-bit adder, and that by knowing the type of operation we can also know what adder type this instruction requires. This is due that there are some types of instruction where one of the two source operands is always narrow. Our approach is based on substituting some of the 64-bit power-hungry adders by others of 32-bit and 24-bits lower power-consumption adders, and modifying the protocol in order to issue as much instructions as possible to those low power-consumption units incurring in a negligible performance penalty. We have tested four different configurations for the execution units in order to find which one obtains a higher reduction on power-consumption, preserving the performance of the processor. Our technique saves between 38,8% and a 54,1% of the power-consumption in the adders which is between 16,6% and a 23,1% of power-consumption in the execution units. This reduction is important because it can avoid the creation of a hot spot on the functional units.

Keywords

Power Consumption Functional Unit Float Point Very Large Scale Integration Program Counter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Guadalupe Miñana
    • 1
  • José Ignacio Hidalgo
    • 1
  • Oscar Garnica
    • 1
  • Juan Lanchares
    • 1
  • José Manuel Colmenar
    • 2
  • Sonia López
    • 1
  1. 1.Departamento de Arquitectura de Computadores y Automática 
  2. 2.Ingeniería Técnica en Informática de SistemasCES Felipe IIUniversidad Complutense de MadridAranjuez MadridSpain

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