Circuit Design Style for Energy Efficiency: LSDL and Compound Domino

  • Xiao Yan Yu
  • Robert Montoye
  • Kevin Nowka
  • Bart Zeydel
  • Vojin Oklobdzija
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)


Introduction of sub-90nm technology has made a profound impact on circuit designs. Thus, it requires understanding of existing design styles for desired energy-efficiency. We compare adder designs in the energy-delay space, implemented with Limited Switch Dynamic Logic (LSDL) and Compound Domino Logic (CD) in a 65nm SOI technology. Evaluation results show that LSDL can provide more than 35% energy savings than CD with 25% switching activity at relaxed cycle times greater than 10.5 FO4.


Critical Path Sparse Tree Transistor Width Logic Family Adder Topology 
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  1. 1.
    Oklobdzija, V.G., et al.: Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders. In: Proceedings of the International Symposium on Computer Arithmetic, ARITH-16, Santiago de Compostela, Spain, June  15-18 (2003)Google Scholar
  2. 2.
    Oklobdzija, V.G., et al.: Comparison of High-Performance VLSI Adders in Energy-Delay Space. IEEE Transaction on VLSI Systems 13(6), 754–758 (2005)CrossRefGoogle Scholar
  3. 3.
    Montoye, R., et al.: A Double Precision Floating Point Multiply, Digest of Technical Papers. In: 2003 IEEE International Solid-State Circuits Conference, San Francisco (February 2003)Google Scholar
  4. 4.
    Houston, T.W., et al.: Compound Domino CMOS Circuit, U.S. Patent No. 5,015,882 (Issued: May 14, 1991)Google Scholar
  5. 5.
    Horowitz, M.: VLSI Scaling for Architects, Presentation slides, Computer Systems Laboratory, Stanford UniversityGoogle Scholar
  6. 6.
    Nowka, K.J.: Issues in High-Performance Processor Design. In: Oklobdzija, V.G. (ed.) The Computer Engineering Handbook. CRC Press Inc., Boca Raton (2002)Google Scholar
  7. 7.
    Interconnect, International Technology Roadmap for Semiconductors (ITRS) (2005) Google Scholar
  8. 8.
    Sutherland, I.E., Sproull, R.F.: Logical Effort: Designing for Speed on the Back of an Envelope. In: Sequin, C.H. (ed.) Advanced Research in VLSI. MIT Press, Cambridge (1991)Google Scholar
  9. 9.
    Kogge, P.M., Stone, H.S.: A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Trans. Computers C-22(8), 786–793 (1973)CrossRefMathSciNetGoogle Scholar
  10. 10.
    Ling, H.: High-Speed Binary Adder. IBM J. Res. Dev. 25, 156–166 (1981)CrossRefGoogle Scholar
  11. 11.
    Park, J., et al.: 470ps 64-bit Parallel Binary Adder. In: Digest of Technical Papers of 2000 Symposium on VLSI Circuits (2000)Google Scholar
  12. 12.
    Mathew, S.K., et al.: Sub-500-ps 64-b ALUs in 0.18-(m SOI/bulk CMOS: design and scaling trends. IEEE Journal of Solid-State Circuits 11 (November 2001)Google Scholar
  13. 13.
    Mathew, S., et al.: A 4-GHZ 130-nm address generation unit with 32-bit sparse-tree adder core. IEEE Journal of Solid-State Circuits 38(5) (May 2003)Google Scholar
  14. 14.
    Mathew, S., et al.: A 4GHZ 300mW 64b Integer Execution ALU with Dual Supply Voltage in 90nm CMOS. Digest of Technical Papers of 2004 IEEE International Solid-State Circuit Conference, San Francisco (February 2004)Google Scholar
  15. 15.
    Shimazaki, Y., et al.: A shared-well dual-supply-voltage 64-bit ALU. IEEE Journal of Solid-State Circuits 39(3) (March 2004)Google Scholar
  16. 16.
    Zeydel, B.R., et al.: Efficient Mapping of Addition Recurrence Algorithms in CMOS. In: 17th IEEE Symposium on Computer Arithmetic, June 27-29 (2005)Google Scholar
  17. 17.
    Dimitrakopoulos, G., Nikolos, D.: High Speed Parallel-Prefix VLSI Ling Adders. IEEE Transactions on Computers (February 2005)Google Scholar
  18. 18.
    Averill, R.M., et al.: Chip Integration Methodology for the IBM S/390 G5 and G6 Custom Microprocessors. IBM Journal of Research and Development 43(5/6) (1999)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Xiao Yan Yu
    • 1
    • 4
  • Robert Montoye
    • 2
  • Kevin Nowka
    • 3
  • Bart Zeydel
    • 4
  • Vojin Oklobdzija
    • 4
  1. 1.IBM PoughkeepsiePoughkeepsieUSA
  2. 2.IBM T.J. Watson Research CenterYorktown HeightsUSA
  3. 3.IBM Austin Research LaboratoryAustinUSA
  4. 4.ACSEL LaboratoryUniversity of CaliforniaDavisUSA

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