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Circuit Design Style for Energy Efficiency: LSDL and Compound Domino

  • Xiao Yan Yu
  • Robert Montoye
  • Kevin Nowka
  • Bart Zeydel
  • Vojin Oklobdzija
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)

Abstract

Introduction of sub-90nm technology has made a profound impact on circuit designs. Thus, it requires understanding of existing design styles for desired energy-efficiency. We compare adder designs in the energy-delay space, implemented with Limited Switch Dynamic Logic (LSDL) and Compound Domino Logic (CD) in a 65nm SOI technology. Evaluation results show that LSDL can provide more than 35% energy savings than CD with 25% switching activity at relaxed cycle times greater than 10.5 FO4.

Keywords

Critical Path Sparse Tree Transistor Width Logic Family Adder Topology 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Xiao Yan Yu
    • 1
    • 4
  • Robert Montoye
    • 2
  • Kevin Nowka
    • 3
  • Bart Zeydel
    • 4
  • Vojin Oklobdzija
    • 4
  1. 1.IBM PoughkeepsiePoughkeepsieUSA
  2. 2.IBM T.J. Watson Research CenterYorktown HeightsUSA
  3. 3.IBM Austin Research LaboratoryAustinUSA
  4. 4.ACSEL LaboratoryUniversity of CaliforniaDavisUSA

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