Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations
In this paper the influence of parameter variations to the effect of power supply noise damping in digital CMOS circuits is investigated. Splitting up the power supply path and using different additional resistors in each path combined with a slight increase of the off-chip supply voltage is found to reduce significantly power supply noise. The damping resistors are optimized using a simulated annealing schedule for the worst-case current waveform. The dependency of this approach to current waveform variations and an increased resistance due to electromigration or a higher operating temperature is examined.
KeywordsSwitching Resistor Current Waveform High Operating Temperature Voltage Variation Additional Resistor
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- 2.Ruehli, A.E.: Inductance calculations in a complex integrated circuit environment. IBM journal of research and development, 470–481 (1972)Google Scholar
- 3.Feldmann, P., Freund, R.W.: Efficient linear circuit analysis by padé approximation via the lanczos process, pp. 170–175 (1994)Google Scholar
- 4.Rauscher, J., Pfleiderer, H.J.: PEEC methods in 2D signal line modeling for mid-frequency on-chip power supply noise simulations. In: 8th IEEE Workshop on Signal Propagation on Interconnects (2004)Google Scholar
- 6.Rauscher, J., Pfleiderer, H.J.: Soc: Simulation and damping of power supply noise. In: SPIE Symp. on Smart Materials, Nano-, and Micro-Smart Systems, Sydney, Australia (2004)Google Scholar
- 7.Rauscher, J., Pfleiderer, H.J.: Power supply noise reduction using additional resistors. In: 9th IEEE Workshop on Signal Propagation on Interconnects, Garmisch-Partenkirchen (2005)Google Scholar
- 8.Mezhiba, A.V., Friedman, E.G.: Power Distribution Networks in High Speed Integrated Circuits. Kluwer Academic Publishers, Dordrecht (2004)Google Scholar