Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations

  • Jürgen Rauscher
  • Hans-Jörg Pfleiderer
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)


In this paper the influence of parameter variations to the effect of power supply noise damping in digital CMOS circuits is investigated. Splitting up the power supply path and using different additional resistors in each path combined with a slight increase of the off-chip supply voltage is found to reduce significantly power supply noise. The damping resistors are optimized using a simulated annealing schedule for the worst-case current waveform. The dependency of this approach to current waveform variations and an increased resistance due to electromigration or a higher operating temperature is examined.


Switching Resistor Current Waveform High Operating Temperature Voltage Variation Additional Resistor 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Jürgen Rauscher
    • 1
  • Hans-Jörg Pfleiderer
    • 1
  1. 1.Department of MicroelectronicsUniversity of UlmUlmGermany

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