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Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOS

  • Saihua Lin
  • Hongli Gao
  • Huazhong Yang
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)

Abstract

By using output control and MTCMOS techniques, we propose two low power low clock swing D flip-flops. Experimental results show that the leakage power of the proposed flip flops can be reduced more than an average of 59% in standby mode and in active mode the total power consumption can be reduced more than an average of 53% while the delay time stays the same. It is also show that the proposed D flip-flops can work even when the clock swing is nearly as low as V dd /3, though the delay time is much increased.

Keywords

Power Reduction Clock Signal Flip Flop Switching Activity Total Power Consumption 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Saihua Lin
    • 1
  • Hongli Gao
    • 1
  • Huazhong Yang
    • 1
  1. 1.Electronic Engineering DepartmentTsinghua UniversityBeijingChina

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