Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOS
By using output control and MTCMOS techniques, we propose two low power low clock swing D flip-flops. Experimental results show that the leakage power of the proposed flip flops can be reduced more than an average of 59% in standby mode and in active mode the total power consumption can be reduced more than an average of 53% while the delay time stays the same. It is also show that the proposed D flip-flops can work even when the clock swing is nearly as low as V dd /3, though the delay time is much increased.
KeywordsPower Reduction Clock Signal Flip Flop Switching Activity Total Power Consumption
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