Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors

  • Oğuz Ergin
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)


Register file is a hot spot in contemporary microprocessors. As the number of instructions present in the processor at a given time increases, the size of the register file increases and it becomes a more important source of power dissipation inside the processor. Therefore it is important to pursue techniques that reduce the energy dissipation of register files. In this paper we present a technique that exploits the narrowness of the produced and consumed values in order to reduce the dynamic energy dissipation of the register file. Our technique results in 20% energy reduction in the integer register file on average.


Energy Efficiency Energy Dissipation Register File Very Large Scale Integration Sense Amplifier 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Borch, E., Tune, E., Manne, S., Emer, J.: Loose Loops Sink Chips. In: Proc. of International Conference on High Performance Computer Architecture (HPCA-8) (2002)Google Scholar
  2. 2.
    Brooks, D., Martonosi, M.: Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance. In: Proc. HPCA (1999)Google Scholar
  3. 3.
    Burger, D., Austin, T.M.: The SimpleScalar tool set: Version 2.0, Tech. Report, Dept. of CS, Univ. of Wisconsin-Madison, and documentation for all Simplescalar releases (through version 3.0) (June 1997)Google Scholar
  4. 4.
    Butts, A., Sohi, G.: Use-Based Register Caching with Decoupled Indexing. In: Proc. of the International Symposium on Computer Architecture (2004)Google Scholar
  5. 5.
    Canal, R., Gonzales, A., Smith, J.: Very Low Power Pipelines using Significance Compression. In: Proc. of the International Symposium on Microarchitecture (2000)Google Scholar
  6. 6.
    Canal, R., Gonzalez, A., Smith, J.: Software-Controlled Operand Gating. In: Proc. of the Intl. Symp. On Code Generation and Optimization (2004)Google Scholar
  7. 7.
    Cruz, J.-L., et al.: Multiple-Banked Register File Architecture. In: Proc. International Symposium on Computer Architecture (ISCA-27), pp. 316–325 (2000)Google Scholar
  8. 8.
    Ergin, O., et al.: Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure. In: MICRO (2004)Google Scholar
  9. 9.
    Gonzalez, R., et al.: A Content Aware Register File Organization. In: ISCA (2004)Google Scholar
  10. 10.
    Hinton, G., et al.: The Microarchitecture of the Pentium 4 Processor. Intel Technology Journal Q1 (2001)Google Scholar
  11. 11.
    Kessler, R.E.: The Alpha 21264 Microprocessor. IEEE Micro 19(2), 24–36 (1999)CrossRefMathSciNetGoogle Scholar
  12. 12.
    Kim, N., Mudge, T.: Reducing Register Ports Using Delayed Write-Back Queues and Operand Pre-Fetch. In: Proc. of Intl. Conference on Supercomputing (ICS-17) (2003)Google Scholar
  13. 13.
    Kondo, M., Nakamura, H.: A Small, Fast and Low-Power Register File by Bit-Partitioning. In: HPCA (2005)Google Scholar
  14. 14.
    Lipasti, M., Mestan, B.R., Gunadi, E.: Physical Register Inlining. In: ISCA (2004)Google Scholar
  15. 15.
    Loh, G.: Exploiting Data-Width Locality to Increase Superscalar Execution Bandwidth. In: Proc. of the International Symposium on Microarchitecture (2002)Google Scholar
  16. 16.
    Loh, G.: Width Prediction for Reducing Value Predictor Size and Power. In: First Value Pred. Wksp., ISCA 2003 (2003)Google Scholar
  17. 17.
    Nakra, T., et al.: Width Sensitive Scheduling for Resource Constrained VLIW Processors. In: Workshop on Feedback Directed and Dynamic Optimizations (2001)Google Scholar
  18. 18.
    Park, I., Powell, M., Vijaykumar, T.: Reducing Register Ports for Higher Speed and Lower Energy. In: Proc. of Intl. Symposium on Microarchitecture (MICRO-35) (2002)Google Scholar
  19. 19.
    Ponomarev, D., Küçük, G., Ergin, O., Ghose, K., Kogge, P.M.: Energy Efficient Issue Queue Design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11(5), 789–800 (2003)CrossRefGoogle Scholar
  20. 20.
    Sato, T., Arita, I.: Table Size Reduction for Data Value Predictors by Exploiting Narrow Width Values. In: Proc. of the International Conference on Supercomputing (2000)Google Scholar
  21. 21.
    Villa, L., Zhang, M., Asanovic, K.: Dynamic Zero Compression for Cache Energy Reduction. In: Micro-33, December (2000)Google Scholar
  22. 22.
    Wallase, S., Bagherzadeh, N.: A Scalable Register File Architecture for Dynamically Scheduled Processors. In: Proc. of International Conference on Parallel Architectures and Compilation Techniques (PACT-5) (1996)Google Scholar
  23. 23.
    Yeager, K.: The MIPS R10000 Superscalar Microprocessor. IEEE Micro 16(2) (April 1996)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Oğuz Ergin
    • 1
  1. 1.Department of Computer ScienceTOBB University of Economics and TechnologySogutozu, AnkaraTurkey

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