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Statistical Characterization of Library Timing Performance

  • V. Migairou
  • R. Wilson
  • S. Engels
  • N. Azemard
  • P. Maurine
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)

Abstract

With the scaling of technology, the variability of timing performances of digital circuits is increasing. In this paper, we propose a first order analytical modeling of the standard deviations of basic CMOS cell timings. The proposed model is then used to define a statistical characterization protocol which is fully compliant with standard characterization flows. Validation of this protocol is given for a 90nm process.

Keywords

Propagation Delay Output Load Statistical Characterization Static Timing Analysis Input Ramp 
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References

  1. 1.
    Visweswariah, C.: Statistical timing of digital integrated circuits. In: IEEE International Solid-State Circuits Conference, CA (2004)Google Scholar
  2. 2.
    Agarwal, A., et al.: Statistical timing analysis for intra-die process variations with spatial correlations. In: ICCAD (2003)Google Scholar
  3. 3.
    Le, J.Y., et al.: STAC: Statistical Timing Analysis with Correlation. In: The Design Automation Conference, June (2004)Google Scholar
  4. 4.
    Orshansky, M., et al.: A general probabilistic framework for worst case timing analysis. In: DAC 2002, pp. 556–561 (2002)Google Scholar
  5. 5.
    Maurine, P., et al.: Transition time modeling in deep submicron CMOS. IEEE Trans. on CAD 21(11), 1352–1363 (2002)Google Scholar
  6. 6.
    Sakurai, T., Newton, A.R.: Alpha-power model, and its application to CMOS inverter delay and other formulas. J. Solid State Circuits 25, 584–594 (1990)CrossRefGoogle Scholar
  7. 7.
    Jeppson, K.O.: Modeling the Influence of the Transistor Gain Ratio and the Input-to-Output Coupling Capacitance on the CMOS Inverter Delay. IEEE JSSC 29, 646–654 (1994)Google Scholar
  8. 8.
    Daga, J.M., et al.: Temperature effect on delay for low voltage applications. In: DATE, Paris, pp. 680–685 (1998)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • V. Migairou
    • 1
  • R. Wilson
    • 1
  • S. Engels
    • 1
  • N. Azemard
    • 2
  • P. Maurine
    • 2
  1. 1.STMicroelectronics Central CAD & Design SolutionCrollesFrance
  2. 2.LIRMMUMR CNRS/Université de Montpellier II, (C5506)MontpellierFrance

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