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Hierarchical Modeling of a Fractional Phase Locked Loop

  • Benjamin Nicolle
  • William Tatinian
  • Jean Oudinot
  • Gilles Jacquemod
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)

Abstract

The aim of this study is to provide a multi level VHDL-AMS modeling of an analog Phase Locked Loop (PLL). Three model levels are described, analyzed and compared in terms of simulation CPU times and accuracy. The characteristic parameters of the PLL, such as the settling time, overshoot, voltage variations linked to charge pump architecture and final voltage are extracted from the intermediate level.

Keywords

Phase Lock Loop Charge Pump Voltage Variation Division Ratio Final Voltage 
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References

  1. 1.
    Nicolle, B., et al.: VHDL-AMS modeling of a multistandard Phase Locked Loop. In: ICECS 2005 Proceeding, pp. 33–36 (2005)Google Scholar
  2. 2.
    Pamarti, Jansson, Galton: A Wideband 2.4GHz Delta Sigma Fractional N PLL with 1Mb/s in loop modulation. IEEE Journal of Solid State Circuits 39(1), 4962 (2004)CrossRefGoogle Scholar
  3. 3.
    Application notes for ADS Software, PLL Transient Response Simulation, Tutorial Google Scholar
  4. 4.
    Allen, P.E.: CMOS phase locked loops Lecture 130 (2003)Google Scholar
  5. 5.
    Juarez-Hernandez, E., Diaz-Sanchez, A.: A novel CMOS charge-pump circuit with positive feedback for PLL applications. In: Electro 2001 (2001)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Benjamin Nicolle
    • 1
    • 2
  • William Tatinian
    • 1
  • Jean Oudinot
    • 2
  • Gilles Jacquemod
    • 1
  1. 1.Laboratoire d’Antennes Electronique et Télécommunications (LEAT)ValbonneFrance
  2. 2.Mentor Graphics FranceSt IsmierFrance

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