Hierarchical Modeling of a Fractional Phase Locked Loop
The aim of this study is to provide a multi level VHDL-AMS modeling of an analog Phase Locked Loop (PLL). Three model levels are described, analyzed and compared in terms of simulation CPU times and accuracy. The characteristic parameters of the PLL, such as the settling time, overshoot, voltage variations linked to charge pump architecture and final voltage are extracted from the intermediate level.
KeywordsPhase Lock Loop Charge Pump Voltage Variation Division Ratio Final Voltage
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