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Optimization of Master-Slave Flip-Flops for High-Performance Applications

  • Raúl Jiménez
  • Pilar Parra
  • Javier Castro
  • Manuel Sánchez
  • Antonio Acosta
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)

Abstract

The design of high-performance master-slave flip-flops is of crucial importance in modern VLSI. The optimization of existing structures is necessary when the requirements of the flip-flop is for low-power, high-speed or low-noise applications. In this work, the optimization via transistor sizing of a well-known master-slave flip-flop is investigated. A detailed analysis of the flip-flop structure provides information useful for optimization, giving an optimum solution for an specific high-performance application.

Keywords

NAND Gate Output Inverter Transistor Level HSPICE Simulation Switching Noise 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Raúl Jiménez
    • 1
  • Pilar Parra
    • 2
  • Javier Castro
    • 2
  • Manuel Sánchez
    • 1
  • Antonio Acosta
    • 2
  1. 1.Dpt. DIESIA, EPS-La RábidaUniversidad de HuelvaHuelvaSpain
  2. 2.Instituto de Microelectrónica de Sevilla/Universidad de SevillaSevillaSpain

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