Abstract
The design of high-performance master-slave flip-flops is of crucial importance in modern VLSI. The optimization of existing structures is necessary when the requirements of the flip-flop is for low-power, high-speed or low-noise applications. In this work, the optimization via transistor sizing of a well-known master-slave flip-flop is investigated. A detailed analysis of the flip-flop structure provides information useful for optimization, giving an optimum solution for an specific high-performance application.
This work has been partially sponsored by the Spanish MEC TEC2004-01509 DOC, the Junta de Andalucía TIC2006-635 and the Universidad de Huelva UHU2004-06 Projects.
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Jiménez, R., Parra, P., Castro, J., Sánchez, M., Acosta, A. (2006). Optimization of Master-Slave Flip-Flops for High-Performance Applications. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_42
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DOI: https://doi.org/10.1007/11847083_42
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