The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing

  • Yijun Liu
  • Steve Furber
  • Zhenkun Li
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)


Power consumption has become one of the most important concerns in the design of embedded processor; the power dissipation of microprocessors grows rapidly as the development of CMOS technology packs more transistors per unit area. However, the potential for further power saving in microprocessors with a conventional architecture is limited because of their unified architectures and mature low-power techniques. An alternative approach to save power is proposed in this paper — embedding a dataflow coprocessor in a conventional RISC processor. The dataflow coprocessor is designed to execute short code segments, such as small loops, function calls and long equation evaluations, very efficiently. We demonstrate a factor of 7 improvement in power-efficiency over current general-purpose processors. Dataflow techniques are not new, but we apply the concept to address a new problem — to improve the power-efficiency of conventional processors.


Clock Cycle Function Block Hierarchical Processing Embed Processor Program Segment 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Yijun Liu
    • 1
  • Steve Furber
    • 2
  • Zhenkun Li
    • 1
  1. 1.The Sensor Network Group, The Faculty of ComputerGuangdong University of TechnologyGuangzhouChina
  2. 2.The Advanced Processor Technologies Group, The School of Computer ScienceThe University of ManchesterManchesterUK

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