Today and more tomorrow, electronic system design requires being concerned with the power issues. Currently, usual design tools consider the application power consumption after RTL synthesis. We propose in this article a FPGA design flow which integrates the power consideration at the early stages. Thus, the designer determines quickly the algorithm and architecture adequacy which respects the design specifications and the power budget.


Power Consumption Power Constraint Architectural Model Power Budget Dynamic Power Consumption 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • David Elléouet
    • 1
  • Yannig Savary
    • 2
  • Nathalie Julien
    • 2
  1. 1.Laboratoire I.E.T.R, UMR CNRS 6164Institut National des Sciences AppliquéesRENNESFrance
  2. 2.Laboratoire L.E.S.T.E.R, FRE CNRS 2734Université de Bretagne SudLorientFrance

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