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Delay Constrained Register Transfer Level Dynamic Power Estimation

  • Sriram Sambamurthy
  • Jacob A. Abraham
  • Raghuram S. Tupuri
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)

Abstract

We present a top-down technique to estimate the average dynamic power consumption of combinational circuits at the register transfer level. The technique also captures the power-delay characteristics of a given combinational circuit. It uses the principles of logical effort to estimate the variation in capacitance, and a combination of existing techniques to estimate the variation in activity, over the delay curve of operation of the circuit. The technique does not involve post-estimation characterization and is applicable across technology nodes. The estimated power obtained from our method shows good accuracy with respect to the power obtained from a commercial gate-level power estimation tool.

Keywords

Power Estimation Output Load Primary Output Combinational Circuit Register Transfer Level 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Sriram Sambamurthy
    • 1
  • Jacob A. Abraham
    • 1
  • Raghuram S. Tupuri
    • 2
  1. 1.Computer Engineering Research CenterThe University of Texas at AustinUSA
  2. 2.Advanced Micro Devices Inc.USA

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