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High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI

  • Masayuki Kitamura
  • Masaaki Iijima
  • Kenji Hamada
  • Masahiro Numa
  • Hiromi Notani
  • Akira Tada
  • Shigeto Maegawa
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)

Abstract

In this paper, we propose a new technique for higher circuit speed without increase in leakage current by using active body-bias controlling technique. Conventional body-bias controlling techniques face difficulties, such as long transition time of body voltage and large area penalty. To overcome these issues, we propose a Charge Recycling Active Body-bias Controlled (CRABC) circuit scheme on SOI which enables quick control of body voltage by using simple additional circuit. The SPICE simulation results have shown that CRABC shortens delay time by 20 %, and transition time for controlling body-bias by 98 %.

Keywords

Leakage Current Logic Circuit Standby Mode Junction Capacitance Junction Diode 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Shahidi, G., Ajmera, A., Assaderaghi, F., Bolam, R., Bryant, A., Coffey, M., Hovel, H., Lasky, J., Leobandung, E., Lo, H.-S., Maloney, M., Moy, D., Rausch, W., Sadana, D., Schepis, D., Sherony, M., Sleight, J.W., Wagner, L.F., Wu, K., Davari, B., Chen, T.C.: Mainstreaming of the SOI Technology. In: 1999 IEEE International SOI Conference, October (1999)Google Scholar
  2. 2.
    Hirano, Y., Ipposhi, T., Dang, H., Matsumoto, T., Iwamatsu, T., Nii, K., Tsukamoto, Y., Kato, H., Maegawa, S., Arimoto, K., Inoue, Y., Inuishi, M., Ohji, Y.: Impact of Active Body-bias Controlled (ABC) SOI SRAM by using Direct Body Contact Technology for Low-Voltage Application. IEDM, Tech. Dig. (December 2003)Google Scholar
  3. 3.
    Kuroda, T., Fujita, T., Mita, S., Nagamatsu, T., Yoshioka, S., Suzuki, K., Sano, F., Norishima, M., Murota, M., Kako, M., Kinugawa, M., Kakumu, M., Sakurai, T.: A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) scheme. IEEE Journal of Solid-State Circuits 31(11), 1770–1779 (1996)CrossRefGoogle Scholar
  4. 4.
    Keshavarzi, A., Narendra, S., Borkar, S., Hawkins, C., Roy, K., De, V.: Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC’s. In: Proceedings of International Symposiumon Low Power Electronics and Design, pp. 252–254 (August 1999)Google Scholar
  5. 5.
    Koura, H., Takamiya, M., Hiramoto, T.: Optimum Condition of Body Effect Factor and Substrate Bias in Variable Threshold Voltage MOSFETs. Jpn. J. Appl. Phys. 39, 2312–2317 (2000)CrossRefGoogle Scholar
  6. 6.
    Hiramoto, T., Takamiya, M., Koura, H., Inukai, T., Gomyo, H., Kawaguchi, H., Sakurai, T.: Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS). Japanese Journal of Applied Physics, Part 1 40(4B), 2854–2858 (2001)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Masayuki Kitamura
    • 1
  • Masaaki Iijima
    • 1
  • Kenji Hamada
    • 1
  • Masahiro Numa
    • 1
  • Hiromi Notani
    • 2
  • Akira Tada
    • 2
  • Shigeto Maegawa
    • 2
  1. 1.Faculty of EngineeringKobe UniversityNada, KobeJapan
  2. 2.Renesas TechnologyItami, HyogoJapan

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