Skip to main content

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 4148))

Abstract

Emerging portable devices relay on DRAM/flash memory system to satisfy requirements on fast and large data storage and low-energy consumption. This paper presents a novel approach to reduce energy of memory system, which unlike others, lowers energy of refresh operation in DRAM. The approach is based on two key ideas: (1) DRAM-based flash cache that keeps dirty pages to reduce the number of accesses to flash memory; and (2) OS-controlled page allocation/aging to stop the refresh operations in banks, whose pages are clean and not accessed for a long time. Simulations show that by using this technique we can decrease the overall energy consumption of DRAM/flash memory on video applications by 8-26% while reducing the DRAM refresh energy by 59-74%.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Weldon, T.: Memory subsystems for 2.5G cellular handsets, Micron Techn. Inc., Jedex, San Jose (2004), http://www.micron.com/products/dram/ddr2sdram/presentation.html

  2. Vargas, O.: Minimum power consumption in mobile phone memory systems, Portable Design (2006)

    Google Scholar 

  3. Lee, H.G., Chang, N.: Low-energy heterogeneous non-volatile memory systems for mobile systems. J. of Low-Power Electronics 1(1), 52–62 (2005)

    Article  Google Scholar 

  4. Samsung Electronics. NAND flash memory & SmartMedia data book (2002)

    Google Scholar 

  5. Park, C., Kang, J.U., Park, S.Y., Kim, J.S.: Energy aware demand paging on NAND flash-based embedded systems. In: Proc. ACM/IEEE Int. Symp. Low-Power Electronics and Design, pp. 338–343

    Google Scholar 

  6. Park, S., Lim, H., Chang, H., Sung, W.: Compressed swapping or NAND flash memory based embedded systems. In: Proc. the IEEE Workshop on Signal Processing Systems (SiPS) (2003)

    Google Scholar 

  7. Samsung Electronics, 128Mb DDR SDRAM Specification, Version 1.0, Rev.1.0 (November 2, 2000)

    Google Scholar 

  8. Lebeck, A.R., Fan, X., Zeng, H., Ellis, C.: Power-aware page allocation. In: Proc. 9th Int. Conf. on Architectural Support for Programming Languages and Operation System (ASPLOS IX) (November 2000)

    Google Scholar 

  9. Fan, X., Zeng, H., Ellis, C., Lebeck, A.R.: Memory controller policies for DRAM power management. In: Proc. ACM/IEEE Int. Symp. Low-Power Electronics and Design (2001)

    Google Scholar 

  10. Delauz, V., et al.: Scheduler-based DRAM energy power management. In: 39th ACM/IEEE DAC, pp. 697–702 (2002)

    Google Scholar 

  11. Huang, H., Shin, K., Lefurgy, C., Keller, T.: Improving Energy efficiency by making DRAM less randomly accessed. In: Proc. ACM/IEEE Int. Symp. Low-Power Electronics and Design (2005)

    Google Scholar 

  12. Ohsawa, T., Kai, K., Murakami, K.: Optimizing the DRAM refresh count for merged DRAM/logic LSIs. In: Proc. ACM/IEEE Int. Symp. Low-Power Electronics and Design, pp. 82–87 (1998)

    Google Scholar 

  13. Hwang, H.-R., Choi, J.-H., Jang, H.-S.: Sysem and method for performing partial array self-refresh operation in a semi-conductor memory device, US Patent, no. 20050041506 (February 24, 2005)

    Google Scholar 

  14. Takahashi, M., et al.: A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM. IEEE J. Solid-State Circuits 35(11), 1713–1721 (2000)

    Article  Google Scholar 

  15. Mobile DRAM: The secret to longer life, MicronTechn. Inc., http://download.micron.com/pdf/flyers/mobile_sdram_flyer.pdf

  16. Huang, H., Pillai, P., Shin, K.G.: Design and implementation of power-aware virtual memory. In: Proceedings of the 2003 USENIX Annual Technical Conf. (June 2003)

    Google Scholar 

  17. Burger, D., Austin, T., Bennet, S.: Evaluating future microprocessors- the superscalar tool set. Technical Report 1306, Univ. of Wisconsin-Madison, CSD (July 1996)

    Google Scholar 

  18. SA-110 Microprocessor, Technical Reference Manual, Intel Corporation (December 2000)

    Google Scholar 

  19. Lee, C., Potkonjak, M., Mangione-Smith, W.-H.: MediaBench: a tool for evaluating and synthesizing multimedia and communication systems. In: Proc. the IEEE Int. Symp. on Microarchitecture (1997)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2006 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Moshnyaga, V.G., Vo, H., Reinman, G., Potkonjak, M. (2006). Handheld System Energy Reduction by OS-Driven Refresh. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_3

Download citation

  • DOI: https://doi.org/10.1007/11847083_3

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-39094-7

  • Online ISBN: 978-3-540-39097-8

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics