Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis

  • Daniel Lima Ferrão
  • Ricardo Reis
  • José Luís Güntzel
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)


Timing analysis of complex state-of-the-art designs demands efficient algorithms able to cope with design complexity. Exploring the hierarchical information generally encountered in complex designs became mandatory to perform functional timing analysis (FTA) in acceptable execution times. Although several hierarchical FTA approaches exist, only path-based hierarchical FTA is able to identify global critical paths, thus helping designers in the optimization task. In this paper we propose two versions of path-based hierarchical FTA strategies. These versions are compared to flat-mode FTA and to commercial FTA tools that operate in hierarchical mode.


Timing Analysis Critical Path Delay Estimate Partial Path Hierarchical Mode 
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  1. 1.
    Chen, H.-C., Du, D.: Path Sensitization in Critical Path Problem. IEEE Transactions on CAD of Integrated Circuits and Systems 12(2), 196–207Google Scholar
  2. 2.
    Devadas, S., Keutzer, K., Malik, S.: Computation of Floating Mode Delay in Combinational Circuits: Theory and Algorithms. IEEE Transactions on Computed-Aided Design of Integrated Circuits and Systems 12(12), 1913–1923Google Scholar
  3. 3.
    Chang, H., Abraham, J.A.: VIPER: An Efficient Vigorously Sensitizable Path Extractor. In: 30th ACM/IEEE Design Automation Conference, pp. 112–117 (1993)Google Scholar
  4. 4.
    Devadas, S., Keutzer, K., Malik, S., Wang, A.: Computation of Floating Mode Delay in Combinational Circuits: Practice and Implementation. IEEE Transactions on Computed-Aided Design of Integrated Circuits and Systems 12(12), 1924–1936Google Scholar
  5. 5.
    Silva, L.G., et al.: Realistic Delay Modeling in Satisfiability-Based Timing Analysis. In: IEEE Intl. Symposium on Circuits & Systems (ISCAS), vol. 6, pp. 215–218 (1998)Google Scholar
  6. 6.
    McGeer, P., et al.: Delay Models and Exact Timing Analysis. In: Sasao, T. (ed.) Logic Synthesis and Optimization, pp. 167–189. Kluwer Academic Pub., Dordrecht (1993)Google Scholar
  7. 7.
    Goel, P.: An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits. IEEE Transactions on Computers C-30(3), 215–222Google Scholar
  8. 8.
    Fujiwara, H., Shimono, T.: On the Acceleration of Test Generation Algorithms. IEEE Transactions on Computers C-32(12), 1137–1144Google Scholar
  9. 9.
    Blaquière, Y., Dagenais, M., Savaria, Y.: Timing Analysis Speed-up Using a Hierarchical and a Multimode Approach. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 15(2), 244–255Google Scholar
  10. 10.
    Heo, S., Kim, J.: Hierarchical Timing Analysis Considering Global False Path. In: Proceedings of ITC-CSCC-2002 (2002)Google Scholar
  11. 11.
    Kukimoto, Y., Brayton, R.K.: Hierarchical Functional Timing Analysis. In: 35th ACM/IEEE Design Automation Conference, pp. 580–585 (1998)Google Scholar
  12. 12.
    Cadence Physically Knowledgeable Synthesis® User Guide. Cadence Design Systems, Inc. (2002)Google Scholar
  13. 13.
    Synopsys PrimeTime® User Guide: Advanced Timing Analysis. Synopsys, Inc. (2004) Google Scholar
  14. 14.
    Yalcin, H., Hayes, J.P.: Hierarchical Timing Analysis Using Conditional Delays. In: Proceedings of International Conference on Computer Aided Design, pp. 371–377 (1995)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Daniel Lima Ferrão
    • 1
  • Ricardo Reis
    • 1
  • José Luís Güntzel
    • 2
  1. 1.UFRGSUniversidade Federal do Rio Grande do Sul, Instituto de InformáticaPorto AlegreBrazil
  2. 2.UFPelUniversidade Federal de Pelotas, Departamento de InformáticaPelotasBrazil

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