Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique

  • B. Chung
  • J. B. Kuo
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)


This paper describes a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis technique for designing high-speed low-power SOC applications using 90nm MTCMOS technology. The cell libraries come in fixed threshold – high Vth for good standby power and low Vth for high-speed. Based on this optimization technique using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less leakage power consumption when compared to the one using only the low-threshold cell library.


Leakage Power Cell Library Static Timing Analysis Timing Violation Multiplier Design 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • B. Chung
    • 1
  • J. B. Kuo
    • 1
  1. 1.School of Eng ScienceSFUBurnabyCanada

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