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Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism

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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (PATMOS 2006)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 4148))

Abstract

The search for energy efficiency in the design of embedded systems is leading toward CPUs with higher instruction-level and data-level parallelism. Unfortunately, individual applications do not have sufficient parallelism to keep all these CPU resources busy. Since embedded systems often consist of multiple tasks, task-level parallelism can be used for the purpose. Simultaneous multi-threading (SMT) proved a valuable technique to do so in high-performance systems, but it cannot be afforded in system with tight energy budgets. Moreover, it does not exploit data-level parallel hardware, and does not exploit the available information on threads.

We propose software-SMT (SW-SMT), a technique to exploit task-level parallelism to improve the utilization of both instruction-level and data-level parallel hardware, thereby improving performance. The technique performs simultaneous compilation of multiple threads at design-time, and it includes a run-time selection of the most efficient mixes.

We have applied the technique to two major blocks of a SDR (software-defined radio) application, achieving energy gains up to 46% on different ILP and DLP architectures. We show that the potentials of SW-SMT increase with SIMD datapath size and VLIW issue width.

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Authors and Affiliations

  1. IMEC vzw, Kapeldreef 75, Heverlee, 3001, Belgium

    Daniele Paolo Scarpazza, Praveen Raghavan, David Novo, Francky Catthoor & Diederik Verkest

  2. Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy

    Daniele Paolo Scarpazza

  3. ESAT, K. U. Leuven, Kasteelpark Arenberg 10, Heverlee, 3001, Belgium

    Praveen Raghavan, David Novo, Francky Catthoor & Diederik Verkest

  4. Electrical Engineering, Vrije Universiteit Brussels, Belgium

    Diederik Verkest

Authors
  1. Daniele Paolo Scarpazza
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  2. Praveen Raghavan
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  3. David Novo
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  4. Francky Catthoor
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  5. Diederik Verkest
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Editor information

Editors and Affiliations

  1. IMEC, Kapeldreef 75, 3001, Heverlee, Belgium

    Johan Vounckx

  2. LIRMM, UMR CNRS/Université de Montpellier II, (C5506), 161 rue Ada, 34392, Montpellier, France

    Nadine Azemard

  3. University of Montpellier / LIRMM, II, 161 rue Ada, 34392, Montpellier, France

    Philippe Maurine

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© 2006 Springer-Verlag Berlin Heidelberg

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Scarpazza, D.P., Raghavan, P., Novo, D., Catthoor, F., Verkest, D. (2006). Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_2

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  • DOI: https://doi.org/10.1007/11847083_2

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-39094-7

  • Online ISBN: 978-3-540-39097-8

  • eBook Packages: Computer ScienceComputer Science (R0)

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