Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology

  • Kenichi Okada
  • Takumi Uezono
  • Kazuya Masu
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)


This paper evaluates the feasibility of on-chip transmission-line interconnect at 45nm CMOS technology. Circuit performances tend to depend heavily on global interconnects, and power and delay of global interconnects are increased due to the miniaturization of process technology. On-chip transmission line has been proposed, which can improve such the large delay and large power consumption of the long RC interconnects. The improvement has been evaluated only for a single interconnect. In this paper, the total power reduction of the entire circuit is evaluated for 45nm technology, which is based on the measurement results at 180nm technology. As an example, the power consumption of global interconnects is improved by 6.6% on a circuit designed for 45nm process.


Power Consumption Transmission Line Power Reduction Wire Length Boundary Length 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Kenichi Okada
    • 1
  • Takumi Uezono
    • 1
  • Kazuya Masu
    • 1
  1. 1.Tokyo Institute of TechnologyYokohamaJapan

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