Abstract
Tomorrow’s embedded devices need to run high-resolution multimedia applications which need an enormous computational complexity with a very low energy consumption constraint. In this context, the register file is one of the key sources of power consumption and its inappropriate design and management can severely affect the performance of the system. In this paper, we present a new approach to reduce the energy of the shared register file in upcoming embedded VLIW architectures with several processing units. Energy savings up to a 60% can be obtained in the register file without any performance penalty. It is based on a set of hardware extensions and a compiler-based energy-aware register assignment algorithm that enable the de/activation of parts of the register file (i.e. sub-banks) in an independent way at run-time, which can be easily included in these embedded architectures.
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References
Wolf, W.: The Future of Multiprocessor Systems-on-Chips. In: Proceedings of DAC (2004)
ST Nomadik Multimedia Processor (2004), http://www.st.com
Philips Nexperia - highly integrated programmable system-on-chip (mpsoc) (2004), http://www.semiconductors.philips.com/products/nexperia
TI’s Omap platform (2004), http://focus.ti.com/omap/docs/
Kim, N.S., Austin, T., Blaauw, D., Mudge, T., Flautner, K., Hu, J., Irwin, M., Kandemir, M., Vijaykrishnan, N.: Leakage current: Moore’s law meets static power. Computer 36(12) (December 2003)
Viredaz, M., Wallacha, D.: Power evaluation of a handheld computer. IEEE Micro 23(1) (January 2003)
Bose, P., Brooks, M.J., Buyuktosunoglu, A., Cook, S., Das, K., Emma, P., Gschwind, M., Jacobson, I., Karkhanis, T., Kudva, P., Schuster, V., Smith, J., Srinivasan, U., Zyuban, V., Albonesi, D.H., Dwarkadas, S.: Early-stage definition of LPX: A low power issue-execute processor. In: Falsafi, B., VijayKumar, T.N. (eds.) PACS 2002. LNCS, vol. 2325, pp. 1–17. Springer, Heidelberg (2003)
Lambrechts, A., Raghavan, P., Leroy, A., Jayapala, M., Vander Aa, T., Catthoor, F., et al.: Power breakdown analysis for a heterogeneous noc platform running a video application. In: Proceedings of ASAP (June 2005)
Abella, J., Gonzalez, A.: On reducing register file pressure and energy in multiple-banked register files. In: Proceedings of ICCD (2003)
Op de Beeck, P., Barat, F., Jayapala, M., Lauwereins, R.: CRISP: A template for reconfigurable instruction set processors. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol. 2147, p. 296. Springer, Heidelberg (2001)
Philips PDSL. Coolflux dsp (2005)
Glokler, T., Meyr, H.: Design of Energy-Efficient Application-Specific Instruction Set Processors. Kluwer Academic Publishers, AH Dordrecht (2002)
Altera. Nios embedded processor system developement (2001)
Gonzalez, R.E.: Xtensa: A configurable and extensible processor. IEEE Micro 20(2) (2002)
Biswas, P., Choudhary, V., Atasu, K., Pozzi, L., Ienne, P., Dutt, N.: Introduction of local memory elements in instruction set extensions. In: Proceedings of DAC (June 2004)
Yu, P., Mitra, T.: Characterizing embedded applications for instruction set extensible processors. In: Proceedings of DAC (June 2004)
Atasu, K., Pozzi, L., Ienne, P.: Automatic application-specific instruction-set extensions under microarchitectural constraints. In: Proceedings of DAC (2003)
Benini, L., Bruni, D., Chinosi, M., Silvano, C., Zaccaria, V., Zafalon, R.: A power modeling and estimation framework for vliw-based embedded systems. In: Proceedings of PATMOS, Yverdon Les Bains, Switzerland (September 2001)
Zyuban, V.V., Kogge, P.M.: The energy complexity of register files. In: Proceedings of ISLPED (1998)
Seznec, A., Toullec, E., Rochecouste, O.: Reducing register ports for higher speed and lower energy. In: Proceedings of MICRO (2002)
Zyuban, V.V., Kogge, P.M.: Inherently lower-power high-performance superscalar architectures. IEEE Transactions on Computers 50(3) (March 2001)
Park, I., Powell, M.D., Vijaykumar, T.N.: Reducing register ports for higher speed and lower energy. In: Proceedings of MICRO (2002)
Koen, J.P., Langendoen, K., Sips, H.J.: Application-directed voltage scaling. IEEE Transactions on Very Large Scale Integration (TVLSI) 11(5) (October 2003)
Akturan, C., Jacome, M.F.: Caliber: A software pipelining algorithm for clustered embedded VLIW processors. In: Proceedings of ICCAD (2001)
Ayala, J.L., López-Vallejo, M., Veidenbaum, A.: Energy-efficient register renaming in high-performance processors. In: Proceedings of WASP (2003)
Ayala, J.L., López-Vallejo, M.: Improving register file banking with a power-aware unroller. In: Proceedings of PARC (2004)
Trimedia Technologies Inc. Trimaran: An infrastructure for research in instruction-level parallelism (1999), http://www.trimaran.org
Raghavan, P., Lambrechts, A., Jayapala, M., Catthoor, F., Verkest, D.: Empirical power model for register files. In: Workshop on Media and Streaming Processors (with MICRO-38) (2005)
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Atienza, D. et al. (2006). Compiler-Driven Leakage Energy Reduction in Banked Register Files. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_11
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DOI: https://doi.org/10.1007/11847083_11
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