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A Time Multiplexing Architecture for Inter-neuron Communications

  • Fergal Tuffy
  • Liam McDaid
  • Martin McGinnity
  • Jose Santos
  • Peter Kelly
  • Vunfu Wong Kwan
  • John Alderman
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4131)

Abstract

This paper presents a hardware implementation of a Time Multiplexing Architecture (TMA) that can interconnect arrays of neurons in an Artificial Neural Network (ANN) using a single metal wire. The approach exploits the relative slow operational speed of the biological system by using fast digital hardware to sequentially sample neurons in a layer and transmit the associated spikes to neurons in other layers. The motivation for this work is to develop minimal area inter-neuron communication hardware. An estimate of the density of on-chip neurons afforded by this approach is presented. The paper verifies the operation of the TMA and investigates pulse transmission errors as a function of the sampling rate. Simulations using the Xilinx System Generator (XSG) package demonstrate that the effect of these errors on the performance of an SNN, pre-trained to solve the XOR problem, is negligible if the sampling frequency is sufficiently high.

Keywords

Hardware Implementation Output Neuron Input Neuron Neuron Layer Firing Time 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Fergal Tuffy
    • 1
  • Liam McDaid
    • 1
  • Martin McGinnity
    • 1
  • Jose Santos
    • 1
  • Peter Kelly
    • 1
  • Vunfu Wong Kwan
    • 2
  • John Alderman
    • 2
  1. 1.Intelligent Systems Engineering Laboratory, School of Computing, and Intelligent Systems, Faculty of EngineeringUniversity of UlsterDerry
  2. 2.Tyndall National InstituteLee Maltings, Prospect RowCorkRep. of Ireland

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