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Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions

  • J. M. Colmenar
  • O. Garnica
  • J. Lanchares
  • J. I. Hidalgo
  • G. Miñana
  • S. Lopez
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4128)

Abstract

In this paper we present sim-async, an architectural simulator able to model a 64-bit asynchronous superscalar microarchitecture. The aim of this tool is to serve the designers on the study of different architectural proposals for asynchronous processors. Sim-async models the data-dependant timing of the processor modules by using distribution functions that describe the probability of a given delay to be spent on a computation. This idea of characterizing the timing of the modules at the architectural level of abstraction using distribution functions is introduced for the first time with this work. In addition, sim-async models the delays of all the relevant hardware involved in the asynchronous communication between stages.

To tackle the development of sim-async we have modified the source code of SimpleScalar by substituting the simulator’s core with our own execution engine, which provides the functionality of a parameterizable microarchitecture adapted to the Alpha ISA. The correctness of sim-async was checked by comparing the outputs of the SPEC2000 benchmarks with SimpleScalar executions, and the asynchronous behavior was successfully tested in relation to a synchronous configuration of sim-async.

Keywords

Execution Engine Architectural Level Asynchronous System SPEC2000 Benchmark Asynchronous Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • J. M. Colmenar
    • 1
  • O. Garnica
    • 2
  • J. Lanchares
    • 2
  • J. I. Hidalgo
    • 2
  • G. Miñana
    • 2
  • S. Lopez
    • 2
  1. 1.C. E. S. Felipe IIComplutense U. of Madrid 
  2. 2.Dept. of Computer Arch. and System EngineeringComplutense U. of Madrid 

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