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Topic 7: Parallel Computer Architecture and Instruction Level Parallelism

  • Eduard Ayguadé
  • Wolfgang Karl
  • Koen De Bosschere
  • Jean-Francois Collard
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4128)

Abstract

We welcome you to the two Parallel Computer Architecture and Instruction Level Parallelism sessions of Euro-Par 2006 conference being held in Dresden, Germany. The call for papers for this Euro-Par topic area sought papers on all hardware/software aspects of parallel computer architecture, processor architecture and microarchitecture. This year 12 papers were submitted to this topic area. Among the submissions, 5 papers were accepted as full papers for the conference (41% acceptance rate).

Keywords

Acceptance Rate Full Paper Register Allocation Instruction Level Parallelism Chip Multiprocessor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Eduard Ayguadé
    • 1
  • Wolfgang Karl
    • 1
  • Koen De Bosschere
    • 1
  • Jean-Francois Collard
    • 1
  1. 1.Topic Chairs 

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