Supporting Cache Locality Optimization with a Toolset
Cache performance significantly influences the computation power of modern processors. With the trend of microprocessor design for both general use and embedded systems towards chip-multiple, cache performance becomes more important because an off-chip access is rather expensive in comparison with on-chip references. This means cache locality optimization remains a hot research area for the next generation of computer architectures.
In this paper we present a tool environment aiming at providing the programmers sufficient support in the task of optimizing source codes for better runtime cache behavior. This environment contains a set of tools ranging from profiling, analysis, and simulation tools for gathering performance data, to visualization tools for graphical presentation and platforms for program development. Together, these tools establish a feedback loop for tuning cache performance on current and emerging uniprocessor and multiprocessor systems.
KeywordsVisualization Tool Access Pattern Cache Line Performance Counter Cache Performance
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- 1.DeRose, L., Ekanadham, K., Hollingsworth, J.K., Sbaraglia, S.: SIGMA: A Simulator Infrastructure to Guide Memory Analysis. In: Supercomputing 2002: Proceedings of the 2002 ACM/IEEE conference on Supercomputing, pp. 1–13 (2002)Google Scholar
- 2.Mohan, T., et al.: Identifying and Exploiting Spatial Regularity in Data Memory References. In: Supercomputing 2003 (November 2003)Google Scholar
- 3.HP. Perfmon Project Web Site, available at http://www.hpl.hp.com/research/linux/perfmon/
- 4.Intel Corporation. Intel Itanium Architecture Software Developer’s Manual, vol. 1–3 (2002), available at http://developer.intel.com/design/itanium/manuals/iiasdmanual.htm
- 8.Rivera, G., Tseng, C.: Tiling Optimizations for 3D Scientific Computations. In: Proceedings of Supercomputing 2000 (2000)Google Scholar
- 9.Shen, X., Gao, Y., Ding, C., Archambault, R.: Lightweight Reference Affinity Analysis. In: ICS 2005: Proceedings of the 19th annual international conference on Supercomputing, New York, pp. 131–140 (2005)Google Scholar
- 11.Yu, Y., Beyls, K., D’Hollander, E.H.: Visualizing the Impact of the Cache on Program Execution. In: Proceedings of the 5th International Conference on Information Visualization (IV 2001), July 2001, pp. 336–341 (2001)Google Scholar