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Code Generation for STA Architecture

  • J. Guo
  • T. Limberg
  • E. Matus
  • B. Mennenga
  • R. Klemm
  • G. Fettweis
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4128)

Abstract

This paper presents a novel compiler backend which generates assembly code for Synchronous Transfer Architecture (STA). STA is a Very Long Instruction Word (VLIW) architecture and in addition it uses a non-orthogonal Instruction Set Architecture (ISA). Generating efficient code for this architecture needs highly optimizing techniques. The compiler backend presented in this paper is based on Integer Linear Programming (ILP). Experimental results show that the generated assembly code consumes much less execution time than the code generated by traditional ways, and the code generation can be accomplished in acceptable time.

Keywords

Execution Time Integer Linear Program Clock Cycle Output Port Basic Block 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • J. Guo
    • 1
  • T. Limberg
    • 1
  • E. Matus
    • 1
  • B. Mennenga
    • 1
  • R. Klemm
    • 1
  • G. Fettweis
    • 1
  1. 1.Vodafone Chair Mobile Communication SystemsTU DresdenGermany

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