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Reductions for Monotone Boolean Circuits

  • Kazuo Iwama
  • Hiroki Morizumi
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4162)

Abstract

The large class, say NLOG, of Boolean functions, including 0-1 Sort and 0-1 Merge, have an upper bound of O(nlogn) for their monotone circuit size, i.e., have circuits with O(nlogn) AND/OR gates of fan-in two. Suppose that we can use, besides such normal AND/OR gates, any number of more powerful “F-gates” which realize a monotone Boolean function F with r (≥2) inputs and r′ (≥1) outputs. Note that the cost of each AND/OR gate is one and we assume that the cost of each F-gate is r. Now we define: A Boolean function f in NLOG is said to be F-Easy if f can be constructed by a circuit with AND/OR/F gates whose total cost is o(nlogn). In this paper we show that 0-1 Merge is not F-Easy for an arbitrary monotone function F such that r′ ≤r/logr.

Keywords

Boolean Function Output Terminal Boolean Circuit Input Terminal Input Gate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Kazuo Iwama
    • 1
  • Hiroki Morizumi
    • 1
  1. 1.Graduate School of InformaticsKyoto UniversityKyotoJapan

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