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Minimizing Generalized Büchi Automata

  • Sudeep Juvekar
  • Nir Piterman
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4144)

Abstract

We consider the problem of minimization of generalized Büchi automata. We extend fair-simulation minimization and delayed-simulation minimization to the case where the Büchi automaton has multiple acceptance conditions. For fair simulation, we show how to efficiently compute the fair-simulation relation while maintaining the structure of the automaton. We then use the fair-simulation relation to merge states and remove transitions. Our fair-simulation algorithm works in time O(mn 3 k 2) where m is the number of transitions, n is the number of states, and k is the number of acceptance sets. For delayed simulation, we extend the existing definition to the case of multiple acceptance conditions. We show that our definition can indeed be used for minimization and give an algorithm that computes the delayed-simulation relation. Our delayed-simulation algorithm works in time O(mn 3 k). We implemented the two algorithms and report on experimental results.

Keywords

Model Check Ranking Function Linear Temporal Logic Winning Strategy Acceptance Condition 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. [AFF+02]
    Armoni, R., Fix, L., Flaisher, A., Gerth, R., Ginsburg, B., Kanza, T., Landver, A., Mador-Haim, S., Singerman, E., Tiemeyer, A., Vardi, M.Y., Zbar, Y.: The ForSpec temporal logic: A new temporal property-specification logic. In: Katoen, J.-P., Stevens, P. (eds.) ETAPS 2002 and TACAS 2002. LNCS, vol. 2280, pp. 211–296. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  2. [BCC+99]
    Biere, A., Cimatti, A., Clarke, E.M., Fujita, M., Zhu, Y.: Symbolic model checking using SAT procedures instead of BDDs. In: 36th DAC, pp. 317–320. IEEE, Los Alamitos (1999)Google Scholar
  3. [BLM01]
    Biesse, P., Leonard, T., Mokkedem, A.: Finding bugs in an alpha microprocessors using satisfiability solvers. In: Berry, G., Comon, H., Finkel, A. (eds.) CAV 2001. LNCS, vol. 2102, pp. 454–464. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  4. [CFF+01]
    Copty, F., Fix, L., Fraer, R., Giunchiglia, E., Kamhi, G., Tacchella, A., Vardi, M.Y.: Benefits of bounded model checking at an industrial setting. In: Berry, G., Comon, H., Finkel, A. (eds.) CAV 2001. LNCS, vol. 2102, pp. 436–453. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  5. [CGP99]
    Clarke, E.M., Grumberg, O., Peled, D.: Model Checking. MIT Press, Cambridge (1999)Google Scholar
  6. [Cho74]
    Choueka, Y.: Theories of automata on ω-tapes: A simplified approach. JCSS 8, 117–141 (1974)MATHMathSciNetGoogle Scholar
  7. [CVWY92]
    Courcoubetis, C., Vardi, M.Y., Wolper, P., Yannakakis, M.: Memory efficient algorithms for the verification of temporal properties. FMSD 1, 275–288 (1992)Google Scholar
  8. [DHW91]
    Dill, D.L., Hu, A.J., Wong-Toi, H.: Checking for language inclusion using simulation relations. In: Larsen, K.G., Skou, A. (eds.) CAV 1991. LNCS, vol. 575, pp. 255–265. Springer, Heidelberg (1992)Google Scholar
  9. [EH00]
    Etessami, K., Holzmann, G.: Optimizing büchi automata. In: Palamidessi, C. (ed.) CONCUR 2000. LNCS, vol. 1877, pp. 153–167. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  10. [EJ91]
    Emerson, E.A., Jutla, C.: Tree automata, μ-calculus and determinacy. In: Proc. 32nd FOCS, pp. 368–377 (1991)Google Scholar
  11. [Eme90]
    Emerson, E.A.: Temporal and modal logic. In: Handbook of TCS (1990)Google Scholar
  12. [EWS01]
    Etessami, K., Wilke, T., Schuller, R.A.: Fair simulation relations, parity games, and state space reduction for Büchi automata. In: Orejas, F., Spirakis, P.G., van Leeuwen, J. (eds.) ICALP 2001. LNCS, vol. 2076, p. 694. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  13. [GBS02]
    Gurumurthy, S., Bloem, R., Somenzi, F.: Fair simulation minimization. In: Brinksma, E., Larsen, K.G. (eds.) CAV 2002. LNCS, vol. 2404, pp. 610–623. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  14. [GH82]
    Gurevich, Y., Harrington, L.: Trees, automata, and games. In: 14th STOC (1982)Google Scholar
  15. [GL94]
    Grumberg, O., Long, D.E.: Model checking and modular verification. ACM TOPLAS 16(3), 843–871 (1994)CrossRefGoogle Scholar
  16. [GO01]
    Gastin, P., Oddoux, D.: Fast LTL to büchi automata translation. In: Berry, G., Comon, H., Finkel, A. (eds.) CAV 2001. LNCS, vol. 2102, pp. 53–65. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  17. [GPVW95]
    Gerth, R., Peled, D., Vardi, M.Y., Wolper, P.: Simple on-the-fly automatic verification of linear temporal logic. In: PSTV, pp. 3–18 (1995)Google Scholar
  18. [HKR97]
    Henzinger, T.A., Kupferman, O., Rajamani, S.: Fair simulation. In: Mazurkiewicz, A., Winkowski, J. (eds.) CONCUR 1997. LNCS, vol. 1243, pp. 273–287. Springer, Heidelberg (1997)Google Scholar
  19. [IEE05]
    IEEE. IEEE standard for property specification language (PSL) (October 2005)Google Scholar
  20. [Jur00]
    JurzińSki, M.: Small progress measures for solving parity games. In: Reichel, H., Tison, S. (eds.) STACS 2000. LNCS, vol. 1770, pp. 290–301. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  21. [KPP05]
    Kesten, Y., Piterman, N., Pnueli, A.: Bridging the gap between fair simulation and trace containment. IC 200(1), 35–61 (2005)MATHMathSciNetGoogle Scholar
  22. [KPV06]
    Kupferman, O., Piterman, N., Vardi, M.Y.: Safraless compositional synthesis. In: Ball, T., Jones, R.B. (eds.) CAV 2006. LNCS, vol. 4144, pp. 31–44. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  23. [KV04]
    Kupferman, O., Vardi, M.Y.: From complementation to certification. In: Jensen, K., Podelski, A. (eds.) TACAS 2004. LNCS, vol. 2988, pp. 591–606. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  24. [McM93]
    McMillan, K.L.: Symbolic Model Checking. Kluwer, Dordrecht (1993)MATHGoogle Scholar
  25. [Mil71]
    Milner, R.: An algebraic definition of simulation between programs. In: Proc. 2nd International Joint Conference on Artificial Intelligence, pp. 481–489 (1971)Google Scholar
  26. [Pnu77]
    Pnueli, A.: The temporal logic of programs. In: 18th FOCS, pp. 46–57 (1977)Google Scholar
  27. [SB00]
    Somenzi, F., Bloem, R.: Efficient Büchi automata from LTL formulae. In: Emerson, E.A., Sistla, A.P. (eds.) CAV 2000. LNCS, vol. 1855, pp. 248–263. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  28. [Str82]
    Streett, R.S.: Propositional dynamic logic of looping and converse. IC 54 (1982)Google Scholar
  29. [Var96]
    Vardi, M.Y.: An automata-theoretic approach to linear temporal logic. In: Moller, F., Birtwistle, G. (eds.) Logics for Concurrency. LNCS, vol. 1043. Springer, Heidelberg (1996)Google Scholar
  30. [VW94]
    Vardi, M.Y., Wolper, P.: Reasoning about infinite computations. IC 115(1) (1994)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Sudeep Juvekar
    • 1
  • Nir Piterman
    • 2
  1. 1.Indian Institute of Technology Bombay 
  2. 2.Ecole Polytechnique Fédéral de Lausanne (EPFL) 

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