Some Complexity Results for SystemVerilog Assertions

  • Doron Bustan
  • John Havlicek
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4144)


SystemVerilog Assertions (SVA) is a linear temporal logic within the recently approved IEEE 1800 SystemVerilog standard. The complexities of the satisfiability and model-checking problems are studied for a basic subset of (SVA) and for extensions of the basic subset obtained by adding each of the following features: local variables, regular expression intersection, quantified variables, and property declarations with arguments. It is shown that the complexities for the basic subset are PSPACE-complete, while the complexities increase to EXPSPACE-complete in each of the extensions. Alternating Büchi automata constructions provide the upper bounds, while reductions from PSPACE and EXPSPACE tiling problems provide the lower bounds.


Local Variable Model Check Regular Expression Linear Temporal Logic Boolean Expression 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Doron Bustan
    • 1
  • John Havlicek
    • 1
  1. 1.Freescale Semiconductor, Inc 

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