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SAT-Based Assistance in Abstraction Refinement for Symbolic Trajectory Evaluation

  • Jan-Willem Roorda
  • Koen Claessen
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4144)

Abstract

We present a SAT-based algorithm for assisting users of Symbolic Trajectory Evaluation (STE) in manual abstraction refinement. As a case study, we demonstrate the usefulness of the algorithm by showing how to refine and verify an STE specification of a CAM.

Keywords

Boolean Expression Satisfying Assignment Delay Element Symbolic Model Check Symbolic Variable 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Aagaard, M., Jones, R.B., Melham, T.F., O’Leary, J.W., Seger, C.-J.H.: A methodology for large-scale hardware verification. In: Johnson, S.D., Hunt Jr., W.A. (eds.) FMCAD 2000. LNCS, vol. 1954, pp. 263–282. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  2. 2.
    Bjesse, P., Leonard, T., Mokkedem, A.: Finding bugs in an Alpha microprocessor using satisfiability solvers. In: Berry, G., Comon, H., Finkel, A. (eds.) CAV 2001. LNCS, vol. 2102, p. 454. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  3. 3.
    Eén, N., Sörensson, N.: An extensible SAT-solver. In: Giunchiglia, E., Tacchella, A. (eds.) SAT 2003. LNCS, vol. 2919, pp. 502–518. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  4. 4.
  5. 5.
    Li, B., Wang, C., Somenzi, F.: Abstraction refinement in symbolic model checking using satisfiability as the only decision procedure. Journal on STTT 7(2), 143–155 (2005)CrossRefGoogle Scholar
  6. 6.
    Melham, T.F., Jones, R.B.: Abstraction by symbolic indexing transformations. In: Aagaard, M.D., O’Leary, J.W. (eds.) FMCAD 2002. LNCS, vol. 2517. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  7. 7.
    Pandey, M., Raimi, R., Bryant, R.E., Abadir, M.S.: Formal verification of content addressable memories using symbolic trajectory evaluation. In: DAC 1997 (1997)Google Scholar
  8. 8.
    Roorda, J.-W.: Symbolic trajectory evaluation using a satisfiability solver. Licentiate thesis, Computing Science, Chalmers University of Technology (2005)Google Scholar
  9. 9.
    Roorda, J.-W., Claessen, K.: A New SAT-Based Algorithm for Symbolic Trajectory Evaluation. In: Borrione, D., Paul, W. (eds.) CHARME 2005. LNCS, vol. 3725, pp. 238–253. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  10. 10.
    Roorda, J.-W., Claessen, K.: Explaining Symbolic Trajectory Evaluation by Giving it a Faithful Semantics. In: Grigoriev, D., Harrison, J., Hirsch, E.A. (eds.) CSR 2006. LNCS, vol. 3967, pp. 555–566. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  11. 11.
    Schubert, T.: High level formal verification of next-generation microprocessors. In: Proceedings of the 40th conference on Design automation, pp. 1–6. ACM Press, New York (2003)Google Scholar
  12. 12.
    Seger, C.-J.H., Bryant, R.E.: Formal verification by symbolic evaluation of partially-ordered trajectories. Formal Methods in System Design 6(2) (1995)Google Scholar
  13. 13.
    Tzoref, R., Grumberg, O.: Automatic Refinement and Vacuity Detection for Symbolic Trajectory Evaluation. In: Ball, T., Jones, R.B. (eds.) CAV 2006. LNCS, vol. 4144, pp. 190–204. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  14. 14.
    Yang, J., Gil, R., Singerman, E.: satGSTE: Combining the abstraction of GSTE with the capacity of a SAT solver. In: Designing Correct Circuits (DCC 2004) (2004)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Jan-Willem Roorda
    • 1
  • Koen Claessen
    • 1
  1. 1.Chalmers University of TechnologySweden

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