An Improved Genetic Algorithm for Cell Placement

  • Guofang Nan
  • Minqiang Li
  • Wenlan Shi
  • Jisong Kou
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4113)


Genetic algorithm, an effective methodology for solving combinatorial optimization problems, is a very computationally expensive algorithm and, as such, numerous researchers have undertaken efforts to improve it. In this paper, we presented the partial mapped crossover and cell move or cells exchange mutation operators in the genetic algorithm when applied to cell placement problem. Traditional initially placement method may cause overlaps between two or more cells, so a heuristic initial placement approach and method of timely updating the coordinates of cells involved were used in order to eliminate overlaps between cells, meanwhile, considering the characters of different circuits to be placed, the punishment item in objective function was simplified. This algorithm was applied to test a set of benchmark circuits, and experiments reveal its advantages in placement results and time performance when compared with the traditional simulated annealing algorithm.


Genetic Algorithm Simulated Annealing Placement Problem Placement Algorithm Placement Method 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Kumar, R., Luo, Z.: Optimizing The Operation Sequence of A Chip Placement Machine Using TSP Model. IEEE Transactions on Electronics Packaging Manufacturing 26(1), 14–21 (2003)CrossRefGoogle Scholar
  2. 2.
    Ishizuka, M., Aida, M.: Achieving Power-law Placement in Wireless Sensor Networks. In: Autonomous Decentralized Systems, 2005. Pro. ISADS 2005, pp. 661–666 (2005)Google Scholar
  3. 3.
    Alrabady, A.L., Mahud, S.M., Chaudhary, V.: Placement of Resources in the Star Network. In: IEEE Second International Conference on Algorithms and Architectures for Parallel Processing ICAPP (1996)Google Scholar
  4. 4.
    Qiu, L., Padmanabhan, V.N., Voelker, G.M.: On the Placement of Web Server Replicas. In: Pro. Twentieth Annual Joint Conference of the IEEE Computer and Communications Societies (INFOCOM 2001), pp. 1587–1596 (2001)Google Scholar
  5. 5.
    John, A.C., Sungho, K.: An Evaluation of Parallel Simulated Annealing Strategies with Application to Standard Cell Placement. IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems 16(3), 398–410 (1997)Google Scholar
  6. 6.
    Terai, M., Takahashi, K., Sato, K.: A New Min-cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length Constrain. In: Design Automation Conference, pp. 96–102 (1990)Google Scholar
  7. 7.
    Saurabh, A., Igor, M., Villarrubia, P.G.: Improving Min-cut Placement for VLSI Using Analytical Techniques. In: IBM ACAS Conference, pp. 55–62 (2003)Google Scholar
  8. 8.
    Quinn, J.R., Breuer, M.A.: A Forced Directed Component Placement Procedure for Printed Circuit Boards. IEEE Trans. CAS 26(6), 377–388 (1979)MATHCrossRefGoogle Scholar
  9. 9.
    Suit, S.M., Youssef, H., Barada, H.R., Al-Yamani, A.: A Parallel Tabu Search Algorithm for VLSI standard-cell placement. In: Proceedings of The 2000 IEEE International Symposium on Circuits and Systems (ISCAS 2000), Geneva, vol. 2, pp. 581–584 (2000)Google Scholar
  10. 10.
    Manikas, T.W., Mickle, M.H.: A genetic Algorithm for Mixed Macro and Standard Cell Placement. Circuits and Systems 2, 4–7 (2002)Google Scholar
  11. 11.
    Shahookar, K., Mazumder, P.: GASP-a Genetic Algorithm for Standard Cell Placement. In: Proceedings of the European Design Automation Conference EDAC 1990, pp. 660–664 (1990)Google Scholar
  12. 12.
    Grover, L.K.: A New Simulated Annealing Algorithm for Standard Cell Placement. In: Proc International Conference on CAD, pp. 378–380 (1986)Google Scholar
  13. 13.
    Esbensen, H., Mazumder, P.: SAGA: A Unification of The Genetic Algorithm with Simulated Annealing and Its Application to Macro-cell placement. In: Proceedings of the Seventh International Conference on VLSI Design, pp. 211–214 (1994)Google Scholar
  14. 14.
    Yao, B., Hou, W., Hong, X., Cai, Y.: FAME: A Fast Detailed Placement Algorithm for Standard Cell Layout Based on Mixed Min-cut and Enumeration. Chinese Journal of Semiconductors 21(8), 744–753 (2000)Google Scholar
  15. 15.
    Nan, G., Li, M., Lin, D., Kou, J.: Adaptive Simulated Annealing for Standard Cell Placement. In: Wang, L., Chen, K., S. Ong, Y. (eds.) ICNC 2005. LNCS, vol. 3612, pp. 943–947. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  16. 16.
    Areibi, S.: The Effect of Clustering and Local Search on Genetic Algorithms. In: Recent Advances In Soft Computing, Leicester, UK, pp. 172–177 (1999)Google Scholar
  17. 17.
    Kim, C.K., Moon, B.R.: Dynamic Embedding for Genetic VLSI Circuit Partitioning. Engineering Applications of Artificial Intelligence, 67–76 (1998)Google Scholar
  18. 18.
    Moon, B.R., Lee, Y.S., Kim, C.K.: GEORG: VLSI Circuit Partitioner with a New Genetic Algorithm Framework. Journal of Intelligent Manufacturing 9, 401–412 (1998)CrossRefGoogle Scholar
  19. 19.
    Nan, G., Li, M., Kou, J.: Two Novel Encoding Strategies Based Genetic Algorithms for Circuit Partitioning. In: Proceedings of 2004 International Conference on Machine Learning and Cybernetics, pp. 2182–2188 (2004)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Guofang Nan
    • 1
  • Minqiang Li
    • 1
  • Wenlan Shi
    • 2
  • Jisong Kou
    • 1
  1. 1.Institute of System EngineeringTianjin UniversityTianjinP.R. China
  2. 2.Department of Information Engineering and AutomatizationHebei Institute of Vocation and TechnologyShijiazhuangChina

Personalised recommendations