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Co-optimization of Performance and Power in a Superscalar Processor Design

  • Yongxin Zhu
  • Weng-Fai Wong
  • Ştefan Andrei
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4097)

Abstract

As process technology scales down, power wall starts to hinder improvements in processor performance. Performance optimization has to proceed under a power constraint. The co-optimization requires exploration into a huge design space containing both performance and power factors, whose size is over costly for extensive traditional simulations. This paper describes a unified model covering both performance and power. The model consists of workload parameters, architectural parameters plus corresponding power parameters with a good degree of accuracy compared with physical processors and simulators. We apply the model to the problem of co-optimizing the power and performance. Concrete insights into the tradeoffs of designs for performance and power are obtained in the process of co-optimization.

Keywords

Power Constraint Dynamic Power Clock Frequency Very Large Scale Integration Leakage Power 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Yongxin Zhu
    • 1
  • Weng-Fai Wong
    • 2
  • Ştefan Andrei
    • 2
  1. 1.School of MicroelectronicsShanghai Jiao Tong University 
  2. 2.School of ComputingNational University of Singapore 

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