Super Semi-systolic Array-Based Application-Specific PLD Architecture
FPGAs have become a critical part of every system design. However, they lag far behind ASICs because of the speed of designs which can be accommodated. Systolic array is an ideal for ASICs because of its massive parallelism with minimum communication overhead, regularity and modularity, but most of commercial FPGAs cannot handle systolic structure with fast sampling rate for their general-purpose architecture nature. Recently, a super-systolic array-based PLD architecture has been proposed. This paper proposes a new PLD architecture targeting a super semi-systolic array — a derivative from a super-systolic array — for application-specific arithmetic operations such as MAC. The proposed super semi-systolic array-based PLD architecture achieves implementation results that are better than those achieved on the super-systolic array-based PLD in terms of hardware complexity and P&R time as well as existing FPGAs in terms of hardware complexity, P&R time and clock speed.
KeywordsLogic Module Logic Unit Arithmetic Operation Systolic Array Hardware Complexity
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