Advertisement

High-Level Synthesis Using SPARK and Systolic Array

  • Jae-Jin Lee
  • Gi-Yong Song
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)

Abstract

Recently, SPARK parallelizing high-level synthesis software tool has been developed. It takes a behavioral ANSI-C code as an input, schedules it using speculative code motions and loop transformations, generates a finite state machine for the scheduled design graph, and then finally outputs a synthesizable RTL VHDL code. To handle loop algorithm, SPARK employs various loop transformations such as loop invariant code motion, loop unrolling, loop index variable elimination and loop shifting. In loop synthesis, however, SPARK does not produce circuit description whose quality can compete with manual designs. With the objective of improving the quality of high-level synthesis results for designs with loops, this paper shows an upgrade of SPARK through transforming nested loops into a 2-D systolic array to increase parallelism. The C-to-VHDL loop synthesis in this paper achieves synthesis results that are better than those achieved from a current version of SPARK for matrix-matrix multiplication and FIR filter, and can be incorporated into SPARK parallelizing high-level synthesis framework.

Keywords

Nest Loop Systolic Array Total Execution Time Hardware Complexity Synthesis Result 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    De Micheli, G.: Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York (1994)Google Scholar
  2. 2.
    Gupta, S., Gupta, R.K., Dutt, N.D., Nicolau, A.: SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits. Kluwer Academic, Dordrecht (2004)Google Scholar
  3. 3.
    Wakabayashi, K., Tanaka,H.: Global scheduling independent of control dependencies based on condition vectors, DAC (1992)Google Scholar
  4. 4.
    Lakshminarayana, G., et al.: Incoporating speculative execution into scheduling of control flow intensive behavioral description, DAC (1998)Google Scholar
  5. 5.
    Behavioral compiler, SynopsysGoogle Scholar
  6. 6.
    Get2Chip Incorporated (now a Cadence subsidiary), G2C architectural compiler, http://www.get2chip.com
  7. 7.
    Forte Design Systems, Behavioral design suit, http://www.forteds.com
  8. 8.
    Gupta, S.: User Manual for the SPARK Parallelizing High-Level Synthesis Framework version 1.1 (2004), http://mesl.ucsd.edu/spark
  9. 9.
    Kung, S.Y.: VLSI Array Processors. Prentice-Hall, Englewood Cliffs (1988)Google Scholar
  10. 10.
    Kung, H.T.: Why Systolic Architectures? IEEE Computers 15(1), 37–46 (1982)CrossRefGoogle Scholar
  11. 11.
    Moldovan, D.I.: ADVIS : A software package for the design of systolic arrays. IEEE Trans. CAD CAD-6(1) (1987)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Jae-Jin Lee
    • 1
  • Gi-Yong Song
    • 1
  1. 1.School of Electrical and Computer EngineeringChungbuk National UniversityCheongjuKorea

Personalised recommendations