Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility
As Moore’s law is loosing steam, one already sees the phenomenon of clock frequency reduction caused by the excessive power dissipation. New technologies that will completely or partially replace silicon are arising, and new architectural alternatives are necessary. Reconfigurable fabric appears to be one of these solutions, and has shown speed ups of critical parts of several data stream programs. However, its wide spread use is still withhold by the need of special tools and compilers, which clearly preclude software portability. Based on all these facts, in this work we propose a coarse-grain dynamic reconfigurable array, tightly coupled to a traditional RISC machine. Besides taking advantage of using combinational logic to speed up the execution, we implement dynamic analysis of the code at run time to reconfigure the array, maintaining full software compatibility. Using the Simplescalar Toolset together with the embedded benchmark suite MIBench, we show performance improvements until 2 times, thanks to the implementation of the proposed approach.
KeywordsBasic Block Combinational Logic Program Counter Main Processor Cache Replacement Policy
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- 2.González, A., Tubella, J., Molina, C.: Trace-Level Reuse. In: Int’l. Conf. on Parallel Processing (September 1999)Google Scholar
- 3.Stitt, G., Lysecky, R., Vahid, F.: Dynamic Hardware/Software Partitioning: A First Approach. In: Design Automation Conference (2003)Google Scholar
- 5.Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B.: MiBench: A Free, Commercially Representative Embedded Benchmark Suite. In: 4th Workshop on Workload Characterization, Austin, TX (December 2001)Google Scholar
- 6.Gwennap, L.: Digital 21264 Sets New Standard. Microprocessor Report 10(14) (Octomber 1996)Google Scholar
- 7.Hauck, S., Fry, T., Hosler, M., Kao, J.: The Chimaera reconfigurable functional unit. In: Proc. IEEE Symp. FPGAs for Custom Computing Machines, Napa Valley, CA, pp. 87–96 (1997)Google Scholar