Skip to main content

A Compiler-Oriented Architecture Description for Reconfigurable Systems

  • Conference paper
Reconfigurable Computing: Architectures and Applications (ARC 2006)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 3985))

Included in the following conference series:

  • 958 Accesses

Abstract

In this paper an architecture description for reconfigurable architectures is introduced which is not limited on a special architecture or a parameterisable template. The main objective is to adapt a compiler from it to cover different reconfigurable architectures. By means of two examples we will illustrate the applicability of our concept.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Tomiyama, H., Halambi, A., Grun, P., Dutt, N., Nicolau, A.: Architecture Description Languages for Systems-on-Chip Design. In: Proceedings of 6th Asia Pacific Conference on Chip Design Languages, pp. 109–116 (1999)

    Google Scholar 

  2. Goldstein, S.C., Schmit, H., Budiu, M., Cadambi, S., Moe, M., Taylor, R.R.: PipeRench: A Reconfigurable Architecture and Compiler. Computer 33(4), 70–77 (2000)

    Article  Google Scholar 

  3. Köhler, S., Braunes, J., Preußer, T., Zabel, M., Spallek, R.G.: Increasing ILP of RISC-Microprocessors through Control-Flow based Reconfiguration. In: Becker, J., Platzner, M., Vernalde, S. (eds.) FPL 2004. LNCS, vol. 3203, pp. 781–790. Springer, Heidelberg (2004)

    Chapter  Google Scholar 

  4. Mei, B.: A Coarse-Grained Reconfigurable Architecture Template and its Compilation Techniques. PhD thesis, Katholieke Universiteit Leuven (2005)

    Google Scholar 

  5. Halambi, A., Grun, P., Ganesh, V., Khare, A., Dutt, N., Nicolau, A.: EXPRESSION: a Language for Architecture Exploration through Compiler/Simulator Retargetability. In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE 1999), pp. 485–490 (1999)

    Google Scholar 

  6. Lee, J., Choi, K., Dutt, N.D.: Compilation Approach for Coarse-Grained Reconfigurable Architectures. IEEE Design and Test of Computers 20, 26–33 (2003)

    Google Scholar 

  7. Preußer, T.B., Köhler, S., Spallek, R.G.: Modelling and Simulating Dynamic and Reconfigurable Architectures for Embedded Computing. In: Proceedings of the 5th EUROSIM Congress on Modeling and Simulation (2004)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2006 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Braunes, J., Spallek, R.G. (2006). A Compiler-Oriented Architecture Description for Reconfigurable Systems. In: Bertels, K., Cardoso, J.M.P., Vassiliadis, S. (eds) Reconfigurable Computing: Architectures and Applications. ARC 2006. Lecture Notes in Computer Science, vol 3985. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11802839_53

Download citation

  • DOI: https://doi.org/10.1007/11802839_53

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-36708-6

  • Online ISBN: 978-3-540-36863-2

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics