Integrating Custom Instruction Specifications into C Development Processes

  • Jack Whitham
  • Neil Audsley
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)


We describe a new approach for creating hardware description language (HDL) specifications for custom instructions, to form part of the instruction-set architecture (ISA) of an application specific instruction set processor (ASIP). Our approach integrates fully into the traditional C development process, binding tightly with software source code and simplifying the ASIP optimisation process. Our tool is also free software, facilitating its use in future research.


Clock Cycle Integrate Development Environment Benchmark Program Manual Implementation Custom Unit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Alomary, A., Nakata, T., Honma, Y., Imai, M., Hikichi, N.: An ASIP instruction set optimization algorithm with functional module sharing constraint. In: Proc. ICCAD, pp. 526–532. IEEE Computer Society Press, Los Alamitos (1993)Google Scholar
  2. 2.
    Anonymous. Nios II Custom Instruction User Guide. Manual UG-N2CSTNST-1.2, Altera Corporation (2004)Google Scholar
  3. 3.
    ARC International. Home page (accessed January 16, 2006),
  4. 4.
    ARC International. Integrated profiler, (accessed 16 January 06),
  5. 5.
    ASIP Meister. Home page, (accessed January 16, 2006),
  6. 6.
    Binh, N.N., Imai, M., Shiomi, A., Hikichi, N.: A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts. In: Proc. DAC, pp. 527–532. ACM Press, New York (1996)Google Scholar
  7. 7.
    Cheung, N., Henkel, J., Parameswaran, S.: Rapid configuration and instruction selection for an ASIP: a case study. In: Proc. DATE, Washington, DC, USA, p. 10802. IEEE Computer Society, Los Alamitos (2003)Google Scholar
  8. 8.
    Coware Corporation. LisaTEK Datasheet (accessed January 16, 2006),
  9. 9.
    Free Software Foundation. GNU Compiler Collection (accessed January 16, 2006),
  10. 10.
    Gonzalez, R.E.: Xtensa — A configurable and extensible processor. IEEE Micro 20(2), 60–70 (2000)MathSciNetCrossRefGoogle Scholar
  11. 11.
    Goodwin, D., Petkov, D.: Automatic generation of application specific processors. In: Proc. CASES, pp. 137–147. ACM Press, New York (2003)Google Scholar
  12. 12.
    Grattan, B., Stitt, G., Vahid, F.: Codesign-extended applications. In: Proc. 10th Int. Symp. Hardware/Software Codesign, pp. 1–6 (2002)Google Scholar
  13. 13.
    Gupta, R.K., Micheli, G.D.: Hardware-software cosynthesis for digital systems. IEEE Des. Test 10(3), 29–41 (1993)CrossRefGoogle Scholar
  14. 14.
    Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B.: Mibench: A free, commercially representative embedded benchmark suite. In: Proc. 4th IEEE Workshop on Workload Characterization (2001)Google Scholar
  15. 15.
    Jain, M.K., Balakrishnan, M., Kumar, A.: ASIP Design Methodologies: Survey and issues. In: Proc. VLSID, Washington, DC, USA, p. 76. IEEE Computer Society, Los Alamitos (2001)Google Scholar
  16. 16.
    Lampret, D.: OpenRISC 1200 (accessed January 16, 2006),
  17. 17.
    Lee, C., Potkonjak, M., Mangione-Smith, W.H.: Mediabench: A tool for evaluating and synthesizing multimedia and communicatons systems. In: Int. Symp. Microarchitecture, pp. 330–335 (1997)Google Scholar
  18. 18.
    Imai, M.: ASIP Meister - DAC participation information (accessed January 16, 2006),
  19. 19.
    Micheli, G.D., Wolf, W., Ernst, R.: Readings in Hardware/Software Co-Design. Morgan Kaufmann Publishers Inc., San Francisco (2001)Google Scholar
  20. 20.
    OAR Corporation. RTEMS (accessed January 16, 2006),
  21. 21.
    Scharwaechter, H., Kammler, D., Wieferink, A., Hohenauer, M., Zeng, J., Karuri, K., Leupers, R., Ascheid, G., Meyr, H.: ASIP Architecture Exploration for Efficient IPSec Encryption: A Case Study. In: Schepers, H. (ed.) SCOPES 2004. LNCS, vol. 3199, pp. 33–46. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  22. 22.
    Sun, F., Ravi, S., Raghunathan, A., Jha, N.K.: Synthesis of custom processors based on extensible platforms. In: Proc. ICCAD, pp. 641–648 (2002)Google Scholar
  23. 23.
    Tensilica Corporation. Home page,
  24. 24.
    Tensilica Corporation. TIE: Product brief (accessed January 16, 2006),
  25. 25.
    Vassiliadis, D., Kavvadias, N., Theodoridis, G., Nikolaidis, S.: A RISC architecture extended by an efficient tightly coupled reconfigurable unit. In: Proc. ARC (2005)Google Scholar
  26. 26.
    Ye, Z.A., Moshovos, A., Hauck, S., Banerjee, P.: Chimaera: a high-performance architecture with a tightly-coupled reconfigurable functional unit. In: Proc. 27th Int. Symp. Computer Architecture, pp. 225–235 (2000)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Jack Whitham
    • 1
  • Neil Audsley
    • 1
  1. 1.Department of Computer ScienceUniversity of YorkYorkUK

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