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Hardware and a Tool Chain for ADRES

  • Bjorn De Sutter
  • Bingfeng Mei
  • Andrei Bartic
  • Tom Vander Aa
  • Mladen Berekovic
  • Jean-Yves Mignolet
  • Kris Croes
  • Paul Coene
  • Miro Cupac
  • Aïssa Couvreur
  • Andy Folens
  • Steven Dupont
  • Bert Van Thielen
  • Andreas Kanstein
  • Hong-Seok Kim
  • Suk Jin Kim
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)

Abstract

Until recently, only a compiler and a high-level simulator of the reconfigurable architecture ADRES existed. This paper focuses on the problems that needed to be solved when moving from a software-only view on the architecture to a real hardware implementation, as well as on the verification process of all involved tools.

Keywords

Loop Body Tool Chain Array Mode VHDL Code Register Rotation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Bjorn De Sutter
    • 1
  • Bingfeng Mei
    • 1
  • Andrei Bartic
    • 1
  • Tom Vander Aa
    • 1
  • Mladen Berekovic
    • 1
  • Jean-Yves Mignolet
    • 1
  • Kris Croes
    • 1
  • Paul Coene
    • 1
  • Miro Cupac
    • 1
  • Aïssa Couvreur
    • 1
  • Andy Folens
    • 1
  • Steven Dupont
    • 1
  • Bert Van Thielen
    • 1
  • Andreas Kanstein
    • 2
  • Hong-Seok Kim
    • 3
  • Suk Jin Kim
    • 3
  1. 1.IMEC vzwBelgium
  2. 2.Freescale Semiconducteurs France SASFrance
  3. 3.Samsung Advanced Institute of TechnologySouth Korea

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