A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware

  • Jie Guo
  • Gleb Belov
  • Gerhard P. Fettweis
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)


Synchronous Transfer Architecture (STA) is a coarse-grain reconfigurable hardware. It is modelled by using a common machine description that is suitable for both compiler and core generator. STA is a Very Long Instruction Word (VLIW) architecture and in addition it uses a non-orthogonal Instruction Set Architecture (ISA). Generating efficient code for such ISA needs highly optimizing techniques. This paper presents a basic data routing Integer Linear Programming (ILP) model for STA code generation. We will also show in this paper, the execution time of the assembly code can be dramatically reduced. The code generation can be accomplished in acceptable time and it can even be real time by reducing the degree of optimality.


Integer Linear Program Output Port Basic Block Direct Data Read Instruction 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Jie Guo
    • 1
  • Gleb Belov
    • 2
  • Gerhard P. Fettweis
    • 1
  1. 1.Vodafone Chair Mobile Communication SystemsT.U. DresdenGermany
  2. 2.Fak. Mathematics and natural sciencesT.U. DresdenGermany

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