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FPGA Implementation of a GF(2m) Tate Pairing Architecture

  • Maurice Keller
  • Tim Kerins
  • Francis Crowe
  • William Marnane
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)

Abstract

This paper presents a hardware implementation of a dual mode Tate pairing/elliptic curve processor over fields of characteristic 2. The architecture can be reconfigured for different underlying field sizes and hence can support different security levels. The processor also performs elliptic curve point scalar multiplication. The performance of the architecture implemented on an FPGA is evaluated for various security levels.

Keywords

Elliptic Curve Clock Cycle Hardware Implementation Security Level FPGA Implementation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Maurice Keller
    • 1
  • Tim Kerins
    • 1
  • Francis Crowe
    • 1
  • William Marnane
    • 1
  1. 1.Dept. of Electrical and Electronic EngineeringUniversity College CorkCork CityIreland

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