Self Reconfiguring EPIC Soft Core Processors

  • Rainer Scholz
  • Klaus Buchenrieder
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)


In this paper, we present a new kind of reconfigurable soft core processor based on the concept of Explicitly Parallel Instruction Computing (EPIC). The implementation targets a dynamic System-on-a-Chip utilizing Field Programmable Gate Arrays. In contrast to established EPIC cores, the number of functional units is adjusted at run-time and depends only on the available resources of the FPGA. Thus, our EPIC core dynamically trades space versus processing performance. Since we employ only standard functional units, we can use off-the-shelf EPIC compilers for efficient code generation.


Functional Unit Field Programmable Gate Array Very Long Instruction Word Instruction Level Parallelism Intellectual Property Core 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Talla, S.: Adaptive explicitly parallel instruction computing. PhD thesis, New York University (2000)Google Scholar
  2. 2.
    Chu, W.W.S., Dimond, R.G., Perrott, S., Seng, S.P., Luk, W.: Customisable EPIC Processor: Architecture and Tools. In: Proc. Conference on Design, Automation and Test in Europe, vol. 3 (2004)Google Scholar
  3. 3.
    Schlansker, M.S., Rau, B.R.: EPIC: An Architecture for Instruction-Level Parallel Processors. HP Laboratories Palo Alto (February 2000)Google Scholar
  4. 4.
    Altera Corporation: Nios Embedded Processor System,
  5. 5.
    Xilinx, Inc.: MicroBlaze Soft Processor Core,
  6. 6.
    Xilinx, Inc.: Virtex-II Platform FPGAs: Complete Data Sheet (March 2005),
  7. 7.
    Xilinx, Inc.: ISE, All the Speed You Need (2005),
  8. 8. Free Open Source IP Cores and Chip Design,
  9. 9.
    Actel Corporation: CoreMP7 - Bringing ARM7 to the Masses,
  10. 10.
    Xilinx, Inc.: Virtex-II Platform FPGA User Guide, p. 297, Internal Configuration Access Port (ICAP) (March 2005),
  11. 11.
    The Trimaran Consortium: An Infrastructure for Research in Instruction-Level Parallelism,
  12. 12.
    Intel Corporation: Intel Itanium 2 Processor,
  13. 13.
    Huck, J., Morris, D., Ross, J., Knies, A., Mulder, H., Zahir, R.: Introducing the IA-64 architecture. IEEE Micro 20(5), 12–23 (2000)CrossRefGoogle Scholar
  14. 14.
    Cofer, R., Harding, B.: FPGA Soft Processor Design Considerations. Programmable Logic DesignLine (October 2005),
  15. 15.
    Celoxica Limited: Platform Developer’s Kit, RC200/203 hardware and PSL Reference Manual (2004),
  16. 16.
    Oregano Systems – Design & Consulting GesmbH: MC8051 IP Core, Oregano Systems 8-bit Microcontroller IP-Core. Version 1.2 (June 2002),

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Rainer Scholz
    • 1
  • Klaus Buchenrieder
    • 1
  1. 1.Universität der Bundeswehr MünchenGermany

Personalised recommendations