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Architecture Based on FPGA’s for Real-Time Image Processing

  • Ignacio Bravo
  • Pedro Jiménez
  • Manuel Mazo
  • José Luis Lázaro
  • Ernesto Martín
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)

Abstract

In this paper an architecture based on FPGA’s for real time image processing is described. The system is composed of a high resolution (1280×1024) CMOS sensor connected to a FPGA that will be in charge of acquiring images from the sensor and controlling it too. A PC sends certain orders and parameters, configured by the user, to the FPGA. The connexion between the PC and the FPGA is made through the parallel port. On the other hand, the resolution of the captured image, as well as the selection of a window of interest inside the image, are configured by the user in the PC. Finally, a system to make the convolution between the captured image and a nxn-mask is shown.

Keywords

Memory Controller Parallel Port CMOS Sensor Digital Image Sensor High Resolution Sensor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Ignacio Bravo
    • 1
  • Pedro Jiménez
    • 1
  • Manuel Mazo
    • 1
  • José Luis Lázaro
    • 1
  • Ernesto Martín
    • 1
  1. 1.Electronics DepartmentUniversity of AlcaláAlcalá de Henares (Madrid)Spain

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