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Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES’ Platform

  • Alex Ngouanga
  • Gilles Sassatelli
  • Lionel Torres
  • Thierry Gil
  • André Borin Suarez
  • Altamiro Amadeu Susin
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)

Abstract

The increasing number of cores used on a single die in response to the power-computing applications tends to orient SoCs more and more toward communication-centric concept. Networks-on-chip (NoC) are good candidates providing both parallelism and flexibility. Nevertheless they imply to consider the notion of locality when distributing the computation among a set of cores. Defining an optimal placement at compile-time is difficult since other applications may temporarily make use of some of the processing resources. This paper explores the opportunity of dynamically mapping task graphs through using different placement algorithms, experiments and comparisons are conducted on a homogeneous coarse-grain reconfigurable architecture running JPEG applications. Results show that run-time task mapping is possible and brings interesting benefits over a random or static placement, especially when contention effects stemming from the communication medium are taken into account.

Keywords

Simulated Annealing Coarse Grained Task Mapping Master Node Task Graph 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Alex Ngouanga
    • 1
  • Gilles Sassatelli
    • 1
  • Lionel Torres
    • 1
  • Thierry Gil
    • 1
  • André Borin Suarez
    • 2
  • Altamiro Amadeu Susin
    • 2
  1. 1.LIRMM – UMR 5506MontpellierFrance
  2. 2.Instituto de Informaica – UFRGSPorto AlegreBrasil

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