QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection

  • Sunil Shukla
  • Neil W. Bergmann
  • Jürgen Becker
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)


To fill the gap between increasing demand for reconfigurability and performance efficiency, CGRAs are seen to be an emerging platform. In this paper, a new architecture, QUKU, is described which uses a coarse-grained reconfigurable PE array (CGRA) overlaid on an FPGA. The low-speed reconfigurability of the FPGA is used to optimize the CGRA for different applications, whilst the high-speed CGRA reconfiguration is used within an application for operator re-use. We will demonstrate the dynamic reconfigurability of QUKU by porting Sobel and Laplacian kernel for edge detection in an image frame.


Edge Detection Edge Detection Algorithm Reconfigurable Architecture Image Edge Detection Laplacian Kernel 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Shukla, S., Bergmann, N., Becker, J.: APEX – A Coarse Grained Reconfigurable Overlay for FPGA. In: Proceedings of the IFIP VLSI SoC, pp. 581–585 (2005)Google Scholar
  2. 2.
    Shukla, S., Bergmann, N., Becker, J.: QUKU: A Two-Level Reconfigurable Architecture. In: ISVLSI 2006 (accepted for presentation, 2006)Google Scholar
  3. 3.
    Alexandro, M., Adário, S., Roehe, E.L., Bampi, S.: Dynamically Reconfigurable Architecture for Image Processor Applications. In: DAC 1999, New Orleans, Louisiana (1999)Google Scholar
  4. 4.
    Hauser, J.R., Wawrzyneck, J.: GARP: A MIPS Processor with a Reconfigurable Coprocessor. In: Proceedings of FCCM, pp. 24–33 (1997)Google Scholar
  5. 5.
    Tsutsui, A., Miyazaki, T.: YARDS: FPGA/MPU Hybrid Architecture for Telecommunication Data Processing. In: Proceedings of FPGA, pp. 93–99 (1997)Google Scholar
  6. 6.
    Wirthlin, M.J., Hutchings, B.L.: DISC: The dynamic instruction set compiler. In: FPGAs for Fast Board Development and Reconfigurable Computing, Proc. SPIE, vol. 2607, pp. 92–103 (1995)Google Scholar
  7. 7.
    Iseli, C., Sanchez, E.: Spyder: A Reconfigurable VLIW processor using FPGAs. In: Proceedings of FCCM, pp. 17–24 (1993)Google Scholar
  8. 8.
    Athanas, P., Silverman, H.F.: Processor Reconfiguration through Instruction Set Metamorphosis. IEEE Computer, pp. 11-18 (March 1993)Google Scholar
  9. 9.
    Guccione, S.: List of FPGA based Computing Machine, online at: http://www.io.com/~guccione/HW_list.html
  10. 10.
    Davis, L.S.: A survey of edge detection techniques. Computer Graphics and Image Processing 4(3), 248–270 (1975)CrossRefGoogle Scholar
  11. 11.
    Nalwa, V.S., Binford, T.O.: On detecting edges. IEEE Transactions on Pattern Analysis and Machine Intelligence PAMI-8(6), 699–714 (1986)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Sunil Shukla
    • 1
    • 2
  • Neil W. Bergmann
    • 1
  • Jürgen Becker
    • 2
  1. 1.ITEEUniversity of QueenslandBrisbaneAustralia
  2. 2.ITIVUniversität KarlsruheKarlsruheGermany

Personalised recommendations