An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects

  • Joong-ho Park
  • Bang-Hyun Sung
  • Seok-Yoon Kim
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)


Up to the present, there have been many works to analyze interconnects on timing aspects, while less works have been done on power aspects. As resistance of interconnects and rise time of signals decrease, power dissipation associated with interconnects is ever-increasing. Hence, an efficient method to compute power dissipation on interconnects is necessary and in this paper we propose a simple yet accurate method to estimate dynamic power dissipation on interconnects. We propose a new reduced-order model to estimate power dissipation on large interconnects. Through the proposed model which is directly derived from total capacitance and resistance of interconnects, we show that the dynamic power dissipation on whole interconnects can be approximated, and propose an analytic method to compute the power dissipation. The results of the proposed method applied to various RC networks show that maximum relative error is within 7% in comparison with HSPICE results.


Power Dissipation Maximum Relative Error Dynamic Power Dissipation Ramp Input Signal Rise Time 
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  1. 1.
    Shin, Y., Sakurai, T.: Power Distribution Analysis of VLSI Interconnects Using Model Order Reduction. IEEE Tran. Computer-Aided Design 21, 739–745 (2002)CrossRefGoogle Scholar
  2. 2.
    Lur, D., Sevensson, C.: Power dissipation Estimation in CMOS VLSI Chips. IEEE Journal of Solid-State Circuits 29, 663–670 (1994)CrossRefGoogle Scholar
  3. 3.
    Micheal, K., Gowan, L.L., Biro, Jackson, D.B.: Power Considerations in the Design of the Alpha 21264 Microprocessor. In: Proc. IEEE DAC (June 1998)Google Scholar
  4. 4.
    Celik, M., Pileggi, L.T., Odabasioglu, A.: IC Interconnect Analysis. Kluwer Academic Publishers, Dordrecht (2002)Google Scholar
  5. 5.
    Rabaey, J.M.: Digital Integrated Circuits, A Design Perspective. Prentice Hall, Inc., New Jersey (2003)Google Scholar
  6. 6.
    Uchino, T., Cong, J.: An Interconnect Energy Model Considering Coupling Effects. In: Proc. IEEE DAC (June 2001)Google Scholar
  7. 7.
    Heydari, P., Pedram, M.: Interconnect Energy Dissipation in High-Speed ULSI Circuit. In: Proc. IEEE Int. Conf. VLSID (2002)Google Scholar
  8. 8.
    O’Brien, P.R., Savarino, T.L.: Modeling the Driving-Point Characteristic of Resistive Interconnect Accurate Delay Estimation. In: Proc. IEEE ICCAD (1989)Google Scholar
  9. 9.
    Kim, S.Y.: Modeling and Analysis of VLSI Interconnects. Sigma Press (1999)Google Scholar
  10. 10.
    Bakoglu, H.B.: Circuit, Interconnections, and Packaging for VLSI. Addison-Wesley, Reading (1990)Google Scholar
  11. 11.
    Gopal, N.: Fast Evaluation of VLSI Interconnect Structures Using Moment-Matching Methods. Ph.D. Thesis, Univ of Texas at Austin (December 1992)Google Scholar
  12. 12.
    Pileggi, L.T., Rohrer, R.A.: Asymptotic Waveform Evaluation for Timing Analysis. IEEE Trans. Computer Aided Design 9 (1990)Google Scholar
  13. 13.
    Odabasioglu, A., Celik, M., Pileggi, L.T.: PRIMA: Passive Reduced Order Interconnect Macromodeling Algorithm. IEEE Tran. Computer Aided Design 18(8), 645–654 (1998)CrossRefGoogle Scholar
  14. 14.
    Acar, E., Odabasioglu, A., Celik, M., Pileggi, L.T.: S2P: A Stable 2-pole RC Delay and Coupling Noise Metric. In: Proc. Great Laked Symposium VLSI (1999)Google Scholar
  15. 15.
    Kal, W.K., Kim, S.Y.: An Analytical Calculation Method for Delay Time of RC-class Interconnect. In: Proc. IEEE ASP-DAC (2000)Google Scholar
  16. 16.
    Khang, A.B.: Muddu: An Analytical Delay Model for VLSI Interconnects under Ramp Input. In: UCLA CS Dept. TR-960015 (1996)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Joong-ho Park
    • 1
  • Bang-Hyun Sung
    • 1
  • Seok-Yoon Kim
    • 1
  1. 1.Department of ComputerSoongsil UniversitySeoulKorea

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