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Register Array Structure for Effective Edge Filtering Operation of Deblocking Filter

  • Jongwoo Bae
  • Neungsoo Park
  • Seong-Won Lee
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4096)

Abstract

In this paper we propose a novel deblocking filter architecture using register array structure for standard video codec hardware. The proposed register array consists of multiple sub-macroblocks for a single macroblock and several sub-macroblock registers for the up and left neighboring macroblocks. The operation procedure of the register array is also presented. The proposed register array achieves fast operating speed and small circuit size at the same time.

Keywords

Internal Memory Shift Operation Filter Operation Hardware Module Deblocking Filter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Jongwoo Bae
    • 1
  • Neungsoo Park
    • 2
  • Seong-Won Lee
    • 3
  1. 1.System LSI DivisionSamsung Electronics, Co. Ltd.SuwonKorea
  2. 2.Dept. of Computer EngineeringKonkuk UniversityKorea
  3. 3.Dept. of Computer EngineeringKwangwoon UniversityKorea

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