Register Array Structure for Effective Edge Filtering Operation of Deblocking Filter
In this paper we propose a novel deblocking filter architecture using register array structure for standard video codec hardware. The proposed register array consists of multiple sub-macroblocks for a single macroblock and several sub-macroblock registers for the up and left neighboring macroblocks. The operation procedure of the register array is also presented. The proposed register array achieves fast operating speed and small circuit size at the same time.
KeywordsInternal Memory Shift Operation Filter Operation Hardware Module Deblocking Filter
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