Power-Aware Instruction Scheduling

  • Tzong-Yen Lin
  • Rong-Guey Chang
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4096)


This paper presents an innovative DVS technique to reduce the energy dissipation. Our objective is to minimize the transitions between power modes by maximizing the idle periods of functional units with instruction scheduling. Our work first analyzes the control flow graph of the application, which contains many regions. Second, we collect the power information and build its power model for each region. Then two regions with the same functional units will be merged if no dependencies exist between them. The process is repeated until no further mergings can be performed. Next, the idle functional units will be turned off and each region will be assigned a power mode based on the power model. Finally, the application is rescheduled to merge the regions to reduce the transitions between power modes. The experimental results show that our work can save the energy by 26%.


Functional Unit Basic Block Power Model Power Mode Idle Period 
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  1. 1.
    AbouGhazaleh, N., Moss’e, D., Childers, B., Melhem, R.: Toward the placement of power management points in real time applications. In: Proceedings of the Workshop on Compilers and Operating Systems for Low Power (September 2001)Google Scholar
  2. 2.
    Alpha, Alpha 21264 Processor Technical Reference Manual,
  3. 3.
    Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A Framework for Architectural Level Power Analysis and Optimizations. In: International Symposium on Computer Architecture (ISCA), Vanconver, British Columbia (2000)Google Scholar
  4. 4.
    Burd, T., Brodersen, R.: Design issues for dynamic voltage scaling. In: Proceedings of 2000 International Symposium on Low Power Electronics and Design (July 2000)Google Scholar
  5. 5.
    Hsu, C.H., Kremer, U.: Compiler-directed dynamic voltage scaling based on program regions. Technical Report DCS-TR-461, Department of Computer Science, Rutgers University (November 2001)Google Scholar
  6. 6.
    Hsu, C.H., Kremer, U.: Single region vs. multiple regions: A comparison of different compiler-directed dynamic voltage scheduling approaches. In: Workshop on Power-Aware Computer Systems (2002)Google Scholar
  7. 7.
    Hsu, C.H., Kremer, U.: The Design, Implementation, and Evaluation of a Compiler Algorithm for CPU Energy Reduction. In: Proceedings of the ACM SIGPLAN Conference on Programming Languages Design and Implementation (June 2003)Google Scholar
  8. 8.
    Krishna, C.M., Lee, Y.-H.: Voltage-clock-scaling adaptive scheduling techniques for low power in hard real-time systems. In: Proceedings of the 6th Real Time Technology and Applications Symposium (RTAS 2000) (May 2000)Google Scholar
  9. 9.
    MachSuif: A Framework built on top of SUIF for building back-ends,
  10. 10.
    Manzak, A., Chakrabarti, C.: Variable voltage task scheduling for minimizing energy or minimizing power. In: Proceeding of the International Conference on Acoustics, Speech and Signal Processing (June 2000)Google Scholar
  11. 11.
    Roy, K.: Leakage Power Reduction in Low-Voltage CMOS Design. In: IEEE International Conference on Circuits and Systems, pp. 167–173 (1998)Google Scholar
  12. 12.
    Sannella, M.J.: Constraint Satisfaction and Debugging for Interactive User Interfaces. Ph.D. Thesis, University of Washington, Seattle, WA (1994)Google Scholar
  13. 13.
    Shin, D., Kim, J., Lee, S.: Intra-task voltage scheduling for low-energy hard real-time applications. IEEE Design and Test of Computers 18(2) (March/April 2001)Google Scholar
  14. 14.
    SUIF: Stanford University Intermediate Format,
  15. 15.
    Transmeta, Crusoe TM5800 Processor Technical Reference Manual,
  16. 16.
    You, Y.-P., Lee, C., Lee, J.K.: Compilers for Leakage Power Reduction. ACM Transactions on Design Automation of Electronic Systems (accepted)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Tzong-Yen Lin
    • 1
  • Rong-Guey Chang
    • 1
  1. 1.Department of Computer ScienceNational Chung Cheng UniversityChia-YiTaiwan

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