Advertisement

Rescheduling for Optimized SHA-1 Calculation

  • Ricardo Chaves
  • Georgi Kuzmanov
  • Leonel Sousa
  • Stamatis Vassiliadis
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4017)

Abstract

This paper proposes the rescheduling of the SHA-1 hash function operations on hardware implementations. The proposal is mapped on the Xilinx Virtex II Pro technology. The proposed rescheduling allows for a manipulation of the critical path in the SHA-1 function computation, facilitating the implementation of a more parallelized structure without an increase on the required hardware resources. Two cores have been developed, one that uses a constant initialization vector and a second one that allows for different Initialization Vectors (IV), in order to be used in HMAC and in the processing of fragmented messages. A hybrid software/hardware implementation is also proposed. Experimental results indicate a throughput of 1.4 Gbits/s requiring only 533 slices for a constant IV and 596 for an imputable IV. Comparisons to SHA-1 related art suggest improvements of the throughput/slice metric of 29% against the most recent commercial cores and 59% to the current academia proposals.

Keywords

Hash Function Critical Path Data Block Initialization Vector Input Message 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Klima, V.: Finding MD5 collisions a toy for a notebook. Cryptology ePrint Archive, Report 2005/075 (2005)Google Scholar
  2. 2.
    Wang, X., Yin, Y.L., Yu, H.: Finding collisions in the full sha-1. In: Shoup, V. (ed.) CRYPTO 2005. LNCS, vol. 3621, pp. 17–36. Springer, Heidelberg (2005)Google Scholar
  3. 3.
    Lien, R., Grembowski, T., Gaj, K.: A 1 gbit/s partially unrolled architecture of hash functions SHA-1 and SHA-512. In: Okamoto, T. (ed.) CT-RSA 2004. LNCS, vol. 2964, pp. 324–338. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  4. 4.
    Sklavos, N., Alexopoulos, E., Koufopavlou, O.G.: Networking data integrity: High speed architectures and hardware implementations. Int. Arab J. Inf. Technol. 1 (2003)Google Scholar
  5. 5.
    Vassiliadis, S., Wong, S., Gaydadjiev, G.N., Bertels, K., Kuzmanov, G.K., Panainte, E.M.: The Molen Polymorphic Processor. IEEE Transactions on Computers 53, 1363–1375 (2004)CrossRefGoogle Scholar
  6. 6.
    NIST: Announcing the standard for secure hash standard, FIPS 180-1. Technical report, National Institute of Standards and Technology (1995)Google Scholar
  7. 7.
    NIST: The keyed-hash message authentication code (HMAC), FIPS 198. Technical report, National Institute of Standards and Technology (2002)Google Scholar
  8. 8.
    CAST: SHA-1 Secure Hash Algorithm Cryptoprocessor Core (2005), http://www.cast-inc.com/
  9. 9.
    HELION: Fast SHA-1 Hash Core for Xilinx FPGA (2005), http://www.heliontech.com/
  10. 10.
    Lu, J., Lockwood, J.: IPSec Implementation on Xilinx Virtex-II Pro FPGA and Its Application. In: Proceedings. 19th IEEE International Parallel and Distributed Processing Symposium, p. 158b (2005)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Ricardo Chaves
    • 1
    • 2
  • Georgi Kuzmanov
    • 2
  • Leonel Sousa
    • 1
  • Stamatis Vassiliadis
    • 2
  1. 1.Instituto Superior TécnicoINESC-IDLisbonPortugal
  2. 2.Computer Engineering LabTUDelftDelftThe Netherlands

Personalised recommendations