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Design of Asynchronous Embedded Processor with New Ternary Data Encoding Scheme

  • Je-Hoon Lee
  • Eun-Ju Choi
  • Kyoung-Rok Cho
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4017)

Abstract

This paper presents a low-power implementation of the asynchronous 8051 processor, called A8051 and it employs a new data encoding method, RT/NRT encoding, to reduce switching activities. The paper focuses on power analysis of the proposed data encoding based on the experimental design of A8051. The proposed data encoding method is devised to meet the DI assumption using Ternary logic. This method reduces not only the number of wires but also the switching activities. In terms of switching activities, the proposed ternary encoding can reduce 26% comparing to conventional ternary encoding. A8051 using RT/NRT encoding shows 24% higher instruction per energy metric comparing to A8051 using dual-rail encoding.

Keywords

Encode Scheme Data Line Switching Activity Pipeline Architecture Invalid State 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Je-Hoon Lee
    • 1
  • Eun-Ju Choi
    • 1
  • Kyoung-Rok Cho
    • 1
  1. 1.Dept. of Computer and Communication Eng.Chungbuk Nat’l Univ.Cheongju-City, Chungbuk-DoRep. of Korea

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